Invention Grant
- Patent Title: Memory effect reduction using low impedance biasing
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Application No.: US15207362Application Date: 2016-07-11
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Publication No.: US09705454B2Publication Date: 2017-07-11
- Inventor: David M. Signoff , Ming He , Wayne A. Loeb
- Applicant: Marvell World Trade, Ltd.
- Applicant Address: BB St. Michael
- Assignee: Marvell World Trade, Ltd.
- Current Assignee: Marvell World Trade, Ltd.
- Current Assignee Address: BB St. Michael
- Main IPC: H03F1/32
- IPC: H03F1/32 ; H03F3/24 ; G05F1/46 ; H03H7/01 ; H03F1/30 ; H03F3/26

Abstract:
A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.
Public/Granted literature
- US20160320781A1 MEMORY EFFECT REDUCTION USING LOW IMPEDANCE BIASING Public/Granted day:2016-11-03
Information query
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