Invention Grant
- Patent Title: Method for wafer etching in deep silicon trench etching process
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Application No.: US14435955Application Date: 2013-12-31
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Publication No.: US09728472B2Publication Date: 2017-08-08
- Inventor: Anna Zhang , Xiaoming Li
- Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.
- Applicant Address: CN
- Assignee: CSMC Technologies FAB1 Co., Ltd.
- Current Assignee: CSMC Technologies FAB1 Co., Ltd.
- Current Assignee Address: CN
- Agency: Widerman Malek, PL
- Agent Mark Malek; Paul J. Ditmyer
- Priority: CN201310011772 20130111
- International Application: PCT/CN2013/091182 WO 20131231
- International Announcement: WO2014/108037 WO 20140717
- Main IPC: H01L21/3065
- IPC: H01L21/3065 ; H01L21/66 ; H01L21/683

Abstract:
A method for wafer etching in a deep silicon trench etching process includes the following steps: a. electrostatically absorbing a wafer using an electrostatic chuck, and stabilizing the atmosphere required by the process (S110); b. performing the sub-steps of a main process for the wafer, and the time for the sub-steps of the main process being shorter than the time required by the wafer main process; c. releasing the electrostatic adsorption of the electrostatic chuck on the wafer; d. determining whether the cumulative time of the sub-steps of the main process reaches a predetermined threshold or not, if so, performing the step e (S150), and if not, repeating the operations in the steps a to c (S140); and e. ending a wafer manufacturing process. The etching method avoids the wafer from continuous contact with the electrostatic chuck, reduces electrostatic accumulation on the surface of the wafer, and therefore solves the problem of resist reticulation on the surface of the wafer in the DSIE process.
Public/Granted literature
- US20150332981A1 METHOD FOR WAFER ETCHING IN DEEP SILICON TRENCH ETCHING PROCESS Public/Granted day:2015-11-19
Information query
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