公开(公告)号：US09431308B2

公开(公告)日：2016-08-30

申请号：US14436033

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Anna Zhang ,  Xiaoming Li

IPC: H01L21/66 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L22/12 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L22/20

Abstract: A critical dimension compensating method of a deep trench etching process includes: obtaining an etching critical dimension difference; compensating an masking layer layout for wafer etching according to a distance between an etching position and the center position of the wafer, and the etching critical dimension difference; and performing a deep trench etching to the wafer according to the compensated masking layer layout. The dimension of the etching patterns of the masking layer layout is compensated by using half of the critical dimension difference as the compensation value, such that the etch rate difference and the etching dimension difference caused by uneven distribution of the critical dimension at different wafer locations during the deep trench etching process are improved, thus greatly improving the uniformity of the critical dimension of the deep trench etching structure.

Abstract translation: 深沟槽蚀刻工艺的关键尺寸补偿方法包括：获得蚀刻临界尺寸差; 根据蚀刻位置和晶片的中心位置之间的距离和蚀刻临界尺寸差补偿用于晶片蚀刻的掩模层布局; 以及根据补偿的掩模层布局对晶片执行深沟槽蚀刻。 通过使用临界尺寸差的一半作为补偿值来补偿掩模层布局的蚀刻图案的尺寸，使得由不同晶片位置的临界尺寸不均匀分布引起的蚀刻速率差和蚀刻尺寸差异 深沟槽蚀刻工艺得到改善，从而大大提高了深沟槽蚀刻结构的临界尺寸的均匀性。

公开(公告)号：US09728472B2

公开(公告)日：2017-08-08

申请号：US14435955

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Anna Zhang ,  Xiaoming Li

IPC: H01L21/3065 ,  H01L21/66 ,  H01L21/683

CPC classification number: H01L22/26 ,  H01L21/3065 ,  H01L21/6831

Abstract: A method for wafer etching in a deep silicon trench etching process includes the following steps: a. electrostatically absorbing a wafer using an electrostatic chuck, and stabilizing the atmosphere required by the process (S110); b. performing the sub-steps of a main process for the wafer, and the time for the sub-steps of the main process being shorter than the time required by the wafer main process; c. releasing the electrostatic adsorption of the electrostatic chuck on the wafer; d. determining whether the cumulative time of the sub-steps of the main process reaches a predetermined threshold or not, if so, performing the step e (S150), and if not, repeating the operations in the steps a to c (S140); and e. ending a wafer manufacturing process. The etching method avoids the wafer from continuous contact with the electrostatic chuck, reduces electrostatic accumulation on the surface of the wafer, and therefore solves the problem of resist reticulation on the surface of the wafer in the DSIE process.