Invention Grant
- Patent Title: Three dimensional stacked semiconductor structure
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Application No.: US14578566Application Date: 2014-12-22
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Publication No.: US09741731B2Publication Date: 2017-08-22
- Inventor: Erh-Kun Lai , Yen-Hao Shih
- Applicant: MACRONIX INTERNATIONAL CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L27/11578
- IPC: H01L27/11578 ; H01L27/11524 ; H01L27/24 ; H01L27/108 ; H01L27/11551 ; H01L27/11529 ; H01L27/06 ; H01L27/02 ; H01L29/78 ; H01L29/792 ; H01L27/11565 ; H01L27/1157

Abstract:
A 3D stacked semiconductor structure is provided, comprising a plurality of stacks vertically formed on a substrate and disposed parallel to each other, a dielectric layer formed on the stacks, a plurality of conductive plugs independently formed in the dielectric layer; and a metal-oxide-semiconductor (MOS) layer formed on the dielectric layer. One of the stacks at least comprises a plurality of multi-layered pillars, and each of the multi-layered pillars comprises a plurality of insulating layers and a plurality of semiconductor layers arranged alternately. The MOS layer comprises a plurality of MOS structures connected to the conductive plugs respectively, and function as layer-selectors for selecting and decoding the to-be-operated layer.
Public/Granted literature
- US20160181269A1 THREE DIMENSIONAL STACKED SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2016-06-23
Information query
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