- 专利标题: Time delayed converter reshuffling
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申请号: US14811033申请日: 2015-07-28
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公开(公告)号: US09748837B1公开(公告)日: 2017-08-29
- 发明人: Selcuk Kose , Orhun Aras Uzun , Weize Yu
- 申请人: UNIVERSITY OF SOUTH FLORIDA
- 申请人地址: US FL Tampa
- 专利权人: UNIVERSITY OF SOUTH FLORIDA
- 当前专利权人: UNIVERSITY OF SOUTH FLORIDA
- 当前专利权人地址: US FL Tampa
- 代理机构: Thomas Horstemeyer, LLP
- 代理商 David R. Risley; Jason M. Perilla
- 主分类号: H02M3/158
- IPC分类号: H02M3/158 ; H02M3/07
摘要:
Dynamic power management techniques and voltage converter architectures are described to provide a secure and efficient on-chip power delivery system. In aspects of the embodiments, converter-gating is used to adaptively turn individual interleaved switched-capacitor stages of a voltage converter on and off based on workload information to improve voltage conversion efficiency. Further, as a countermeasure against machine learning based differential power analysis attacks, for example, control signals provided to a number of the interleaved switched-capacitor stages are delayed to reduce the risk of low power trace entropy (PTE). A higher PTE value is maintained regardless of the phase difference between an attacker's sampling rate and the operating frequency, providing an additional layer of security.
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