Invention Grant
- Patent Title: Memory protection with non-readable pages
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Application No.: US14583681Application Date: 2014-12-27
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Publication No.: US09753863B2Publication Date: 2017-09-05
- Inventor: Rekha N. Bachwani , Ravi L. Sahita , David M. Durham
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/14

Abstract:
A method includes, in various implementations, regulating a memory region for execute-only access, storing a set of instructions in the memory region, executing an early instruction among the set of instructions, and executing a set of subsequent instructions among the instructions. The early instruction loads a secret value into a volatile register. A correct execution of the subsequent instructions depends on the secret value being loaded into the volatile register.A system includes, in various implementations, a memory and a processor with one or more volatile registers. The processor regulates access to portions of the memory. The processor can load a secret value into the volatile register in response to executing a program stored in an execute-only portion of the memory. The processor is configured to lose, in response to an asynchronous event, information loaded in the volatile registers.
Public/Granted literature
- US20160188492A1 Memory Protection with Non-Readable Pages Public/Granted day:2016-06-30
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