Invention Grant
- Patent Title: Multi-level stacked transistor device including capacitor and different semiconductor materials
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Application No.: US13755921Application Date: 2013-01-31
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Publication No.: US09755084B2Publication Date: 2017-09-05
- Inventor: Atsuo Isobe , Yasuyuki Arai
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2012-026737 20120209
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L27/12

Abstract:
A semiconductor device having a novel structure is provided in which a transistor including an oxide semiconductor and a transistor including a semiconductor material which is not an oxide semiconductor are stacked. Further, a semiconductor device in which a semiconductor element and a capacitor are formed efficiently is provided. In a semiconductor device, a first semiconductor element layer including a transistor formed using a semiconductor material which is not an oxide semiconductor, such as silicon, and a second semiconductor element layer including a transistor formed using an oxide semiconductor are stacked. A capacitor is formed using a wiring layer, or a conductive film or an insulating film which is in the same layer as a conductive film or an insulating film of the second semiconductor element layer.
Public/Granted literature
- US20130207112A1 SEMICONDUCTOR DEVICE Public/Granted day:2013-08-15
Information query
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