公开(公告)号：US10522689B2

公开(公告)日：2019-12-31

申请号：US15605211

申请日：2017-05-25

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Toshinari Sasaki ,  Hitomi Sato ,  Kosei Noda ,  Yuta Endo ,  Mizuho Ikarashi ,  Keitaro Imai ,  Atsuo Isobe ,  Yutaka Okazaki

IPC分类号： H01L29/786 ,  H01L29/66

摘要： It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.

公开(公告)号：US10366885B2

公开(公告)日：2019-07-30

申请号：US15350777

申请日：2016-11-14

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Koichiro Tanaka ,  Hidekazu Miyairi ,  Aiko Shiga ,  Akihisa Shimomura ,  Atsuo Isobe

IPC分类号： H01L21/02 ,  H01L21/283 ,  B23K26/352 ,  B23K26/06 ,  B23K26/073 ,  H01L27/12 ,  H01L21/268 ,  B23K101/40 ,  H01L27/146

摘要： The present invention is characterized in that by laser beam being slantly incident to the convex lens, an aberration such as astigmatism or the like is occurred, and the shape of the laser beam is made linear on the irradiation surface or in its neighborhood. Since the present invention has a very simple configuration, the optical adjustment is easier, and the device becomes compact in size. Furthermore, since the beam is slantly incident with respect to the irradiated body, the return beam can be prevented.

公开(公告)号：US10361222B2

公开(公告)日：2019-07-23

申请号：US15897318

申请日：2018-02-15

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Atsuo Isobe ,  Shunpei Yamazaki ,  Koji Dairiki ,  Hiroshi Shibata ,  Chiho Kokubo ,  Tatsuya Arao ,  Masahiko Hayakawa ,  Hidekazu Miyairi ,  Akihisa Shimomura ,  Koichiro Tanaka ,  Mai Akiba

IPC分类号： H04L27/12 ,  H01L27/12 ,  H01L21/3213 ,  H01L21/02 ,  B23K26/073 ,  H01L21/20 ,  H01L21/84 ,  H01L29/66 ,  H01L29/786

摘要： A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formulation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.

公开(公告)号：US09704882B2

公开(公告)日：2017-07-11

申请号：US15199004

申请日：2016-06-30

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Wataru Uesugi ,  Hikaru Tamura ,  Atsuo Isobe

IPC分类号： H03K19/00 ,  H01L27/12 ,  H01L49/02 ,  H01L29/04 ,  H01L29/78 ,  H03K19/0185 ,  G11C7/04

CPC分类号： H01L27/1207 ,  G11C7/04 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7849 ,  H01L29/78648 ,  H01L29/78696 ,  H03K19/0008 ,  H03K19/018514

摘要： A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US09559193B2

公开(公告)日：2017-01-31

申请号：US14576400

申请日：2014-12-19

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Atsuo Isobe ,  Toshinari Sasaki ,  Shinya Sasagawa ,  Akihiro Ishizuka

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/477 ,  H01L29/04 ,  H01L29/24

CPC分类号： H01L29/66969 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/477 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/7869

摘要： A semiconductor device having a transistor including an oxide semiconductor film is disclosed. In the semiconductor device, the oxide semiconductor film is provided along a trench formed in an insulating layer. The trench includes a lower end corner portion and an upper end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, the upper end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the upper end corner portion.

摘要翻译： 公开了一种具有包括氧化物半导体膜的晶体管的半导体器件。 在半导体装置中，沿着形成在绝缘层中的沟槽设置氧化物半导体膜。 沟槽包括具有曲率半径大于或等于20nm且小于或等于60nm的弯曲形状的下端拐角部分和上端拐角部分，并且氧化物半导体膜设置成与 底面，下端角部，上端角部和沟槽的内壁面。 氧化物半导体膜包括至少在上端角部上方具有基本上垂直于表面的c轴的晶体。

公开(公告)号：US09472656B2

公开(公告)日：2016-10-18

申请号：US14837565

申请日：2015-08-27

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Atsuo Isobe ,  Yoshinori Ieda ,  Masaharu Nagai

IPC分类号： H01L21/84 ,  H01L29/66 ,  H01L29/786 ,  H01L29/417

CPC分类号： H01L29/66969 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/7869

摘要： A semiconductor device including a minute transistor with a short channel length is provided. A gate insulating layer is formed over a gate electrode layer; an oxide semiconductor layer is formed over the gate insulating layer; a first conductive layer and a second conductive layer are formed over the oxide semiconductor layer; a conductive film is formed over the first conductive layer and the second conductive layer; a resist mask is formed over the conductive film by performing electron beam exposure; and then a third conductive layer and a fourth conductive layer are formed over and in contact with the first conductive layer and the second conductive layer, respectively, by selectively etching the conductive film.

摘要翻译： 提供了包括具有短沟道长度的微小晶体管的半导体器件。 在栅电极层上形成栅极绝缘层; 在栅绝缘层上形成氧化物半导体层; 在所述氧化物半导体层上形成第一导电层和第二导电层; 在第一导电层和第二导电层上形成导电膜; 通过进行电子束曝光在导电膜上形成抗蚀剂掩模; 然后通过选择性地蚀刻导电膜，分别在第一导电层和第二导电层上形成第三导电层和第四导电层，并与第二导电层接触。

公开(公告)号：US09466622B2

公开(公告)日：2016-10-11

申请号：US14995442

申请日：2016-01-14

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Hiroshi Shibata ,  Atsuo Isobe

IPC分类号： H01L27/00 ,  H01L27/12 ,  H01L27/32 ,  G02F1/1345 ,  G02F1/1362 ,  H01L29/786 ,  G02F1/1333 ,  G02F1/1368 ,  H01L29/49

CPC分类号： H01L27/1255 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136277 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/3244 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78633

摘要： To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.

摘要翻译： 为了提供一种通过在确保足够的存储电容器（Cs）的同时获得高开口率而具有高质量显示的液晶显示装置，并且同时通过分散电容器布线的负载（像素写入电流） 及时有效减轻负荷。 扫描线形成在与栅电极不同的层上，电容布线与信号线平行。 每个像素通过电介质连接到单独独立的电容器布线。 因此，可以避免由相邻像素的写入电流引起的电容器布线的电位变化，从而获得令人满意的显示图像。

公开(公告)号：US09385713B2

公开(公告)日：2016-07-05

申请号：US14874607

申请日：2015-10-05

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Wataru Uesugi ,  Hikaru Tamura ,  Atsuo Isobe

IPC分类号： H03K19/00 ,  H03K19/0185 ,  H01L29/78 ,  H01L29/04 ,  H01L27/12 ,  H01L49/02

CPC分类号： H01L27/1207 ,  G11C7/04 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7849 ,  H01L29/78648 ,  H01L29/78696 ,  H03K19/0008 ,  H03K19/018514

摘要： A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

摘要翻译： 逻辑电路中提供的保持电路使能电源门控。 保持电路包括第一端子，节点，电容器以及第一至第三晶体管。 第一晶体管控制逻辑电路的第一端子和输入端子之间的电连接。 第二晶体管控制逻辑电路的输出端和节点之间的电连接。 第三晶体管控制节点与逻辑电路的输入端之间的电连接。 第一晶体管的栅极电连接到第二晶体管的栅极。 在数据保留期间，节点变为电浮动。 节点的电压由电容器保持。

公开(公告)号：US09087855B2

公开(公告)日：2015-07-21

申请号：US14474516

申请日：2014-09-02

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Atsuo Isobe ,  Toshinari Sasaki ,  Junichi Koezuka ,  Shunpei Yamazaki

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/66 ,  H01L21/84 ,  H01L27/108 ,  H01L27/115 ,  H01L27/12 ,  H01L49/02 ,  H01L29/786 ,  H01L21/425 ,  H01L21/02

CPC分类号： H01L29/4238 ,  H01L21/02565 ,  H01L21/265 ,  H01L21/425 ,  H01L21/84 ,  H01L27/1085 ,  H01L27/10876 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78693

摘要： It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.

摘要翻译： 本发明的目的是提供一种抑制短路效应并实现小型化的半导体器件及其制造方法。 在绝缘层中形成沟槽，并且将杂质添加到与沟槽的上端角部接触的氧化物半导体膜，由此形成源极区域和漏极区域。 利用上述结构，可以实现小型化。 此外，利用沟槽，即使当源电极层和漏电极层之间的距离缩短时，也可以适当地抑制沟槽的深度适当地设定短沟道效应。

公开(公告)号：US09029863B2

公开(公告)日：2015-05-12

申请号：US13860894

申请日：2013-04-11

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Atsuo Isobe

IPC分类号： H01L29/12 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L29/66969 ,  H01L21/70 ,  H01L27/1085 ,  H01L27/1259 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

摘要： A variation in electrical characteristics, such as a negative shift of the threshold voltage or an increase in S value, of a fin-type transistor including an oxide semiconductor material is prevented. An oxide semiconductor film is sandwiched between a plurality of gate electrodes with an insulating film provided between the oxide semiconductor film and each of the gate electrodes. Specifically, a first gate insulating film is provided to cover a first gate electrode, an oxide semiconductor film is provided to be in contact with the first gate insulating film and extend beyond the first gate electrode, a second gate insulating film is provided to cover at least the oxide semiconductor film, and a second gate electrode is provided to be in contact with part of the second gate insulating film and extend beyond the first gate electrode.

摘要翻译： 防止包括氧化物半导体材料的鳍式晶体管的电特性的变化，例如阈值电压的负偏移或S值的增加。 氧化物半导体膜被夹在多个栅电极之间，其间具有设置在氧化物半导体膜和每个栅电极之间的绝缘膜。 具体地，设置第一栅极绝缘膜以覆盖第一栅电极，设置氧化物半导体膜以与第一栅极绝缘膜接触并且延伸超过第一栅电极，设置第二栅极绝缘膜以覆盖在 至少设置氧化物半导体膜，第二栅电极与第二栅极绝缘膜的一部分接触并且延伸超过第一栅电极。