Invention Grant
- Patent Title: Wafer level package and fabrication method thereof
-
Application No.: US14927491Application Date: 2015-10-30
-
Publication No.: US09761540B2Publication Date: 2017-09-12
- Inventor: Shing-Yih Shih
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/00 ; H01L23/498 ; H01L23/367 ; H01L23/373 ; H01L23/16 ; H01L21/56 ; H01L23/31
Abstract:
A semiconductor device that includes a redistribution layer (RDL) is disclosed. A chip is mounted on the RDL within a chip mounting area. The RDL is electrically connected to the chip. A molding compound covers and encapsulates the chip. A first stress-relief feature is embedded in the molding compound within a peripheral area adjacent to the chip mounting area. A second stress-relief feature is embedded in the molding compound within the chip mounting area. The first stress-relief feature is composed of a first material. The second stress-relief feature is composed of a second material that is different from the first material.
Public/Granted literature
- US20160379935A1 WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF Public/Granted day:2016-12-29
Information query
IPC分类:
