公开(公告)号：US10566229B2

公开(公告)日：2020-02-18

申请号：US15910360

申请日：2018-03-02

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang ,  Neng-Tai Shih

IPC: H01L21/683 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/78

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

公开(公告)号：US20180366540A1

公开(公告)日：2018-12-20

申请号：US16110615

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Tieh-Chiang Wu ,  Shing-Yih Shih

IPC: H01L49/02 ,  H01L23/48 ,  H01L21/768 ,  H01L21/3065 ,  C23C14/10 ,  C23C14/08 ,  C23C14/06 ,  C23C16/06 ,  C23C16/34 ,  H01L29/66 ,  C23C16/40 ,  C23C14/16 ,  H01L29/92 ,  H01L21/304 ,  H01L21/306

Abstract: A semiconductor structure and a method of fabricating thereof are provided. The method includes the following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess.

公开(公告)号：US10008461B2

公开(公告)日：2018-06-26

申请号：US14731426

申请日：2015-06-05

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/05578 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/10125 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/01074

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

公开(公告)号：US20180102313A1

公开(公告)日：2018-04-12

申请号：US15291086

申请日：2016-10-12

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A molded interposer includes a layer of first molding compound having a first side and a second side opposite to the first side; a first redistribution layer (RDL) structure disposed on the first side; a second redistribution layer (RDL) structure disposed on the second side; a plurality of metal vias embedded in the layer of first molding compound for electrically connecting the first RDL structure with the second RDL structure; and a passive device embedded in the layer of first molding compound.

公开(公告)号：US20180102311A1

公开(公告)日：2018-04-12

申请号：US15286582

申请日：2016-10-06

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

Abstract: A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure integrally constructed on the silicon substrate portion, and TSVs in the silicon substrate portion. A first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure. The first semiconductor die and the second semiconductor die are coplanar.

公开(公告)号：US09761559B1

公开(公告)日：2017-09-12

申请号：US15135539

申请日：2016-04-21

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/48 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L2224/16145 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06558 ,  H01L2225/06586

Abstract: A semiconductor package includes a first logic die, a second logic die disposed in close proximity to the first logic die, a bridge memory die coupled to both the first logic die and the second logic die, a redistribution layer (RDL) structure coupled to the first logic die and the second logic die, and a molding compound at least partially encapsulating the first logic die, the second logic die, and the bridge memory die. The first logic die and the second logic die are coplanar.

公开(公告)号：US11735540B2

公开(公告)日：2023-08-22

申请号：US17177431

申请日：2021-02-17

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Neng-Tai Shih

IPC: H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/29 ,  H01L25/00

CPC classification number: H01L24/02 ,  H01L21/6835 ,  H01L23/562 ,  H01L24/97 ,  H01L25/0655 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/83

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

公开(公告)号：US11710693B2

公开(公告)日：2023-07-25

申请号：US17110035

申请日：2020-12-02

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/19 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/3511 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Semiconductor packages may include a molded interposer and semiconductor dice mounted on the molded interposer. The molded interposer may include two redistribution layer structures on opposite sides of a molding compound. Electrically conductive vias may connect the RDL structures through the molding compound, and passive devices may be embedded in the molding compound and electrically connected to one of the RDL structures. Each of the semiconductor dice may be electrically connected to, and have a footprint covering, a corresponding one of the passive devices to form a face-to-face connection between each of the semiconductor dice and the corresponding one of the passive devices.

公开(公告)号：US10833052B2

公开(公告)日：2020-11-10

申请号：US15286582

申请日：2016-10-06

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  H01L23/14

Abstract: A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure integrally constructed on the silicon substrate portion, and TSVs in the silicon substrate portion. A first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure. The first semiconductor die and the second semiconductor die are coplanar.

公开(公告)号：US10825783B2

公开(公告)日：2020-11-03

申请号：US16021383

申请日：2018-06-28

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538

Abstract: Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor chips over a top side of a wafer, molding the plurality of semiconductor chips with a first molding material, and after molding the semiconductor chips, forming a composite layer over the plurality of semiconductor chips.