Invention Grant
- Patent Title: Metal-oxide-semiconductor transistor and method of forming gate layout
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Application No.: US14952877Application Date: 2015-11-25
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Publication No.: US09761657B2Publication Date: 2017-09-12
- Inventor: Shih-Yin Hsiao , Ching-Chung Yang , Wen-Fang Lee , Nien-Chung Li , Chih-Chung Wang
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: TW104133652A 20151014
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/78 ; G06F17/50 ; H01L23/535
Abstract:
A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v.
Public/Granted literature
- US20170110536A1 METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FORMING GATE LAYOUT Public/Granted day:2017-04-20
Information query
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