In an example, the present invention includes an integrated system on chip device. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. In an example, the data input/output interface is configured for number of lanes numbered from four to one hundred and fifty. In an example, the SerDes block is configured to convert a first data stream of N into a second data stream of M such that each of the first data stream having a first predefined data rate at a first clock rate and each of the second data stream having a second predefined data rate at a second clock rate.