Invention Grant
- Patent Title: Semiconductor device having barrier region and edge termination region enclosing barrier region
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Application No.: US15089542Application Date: 2016-04-02
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Publication No.: US09773924B2Publication Date: 2017-09-26
- Inventor: Masao Uchida , Kouichi Saitou , Takayuki Wakayama
- Applicant: Panasonic Intellectual Property Management Co., Ltd.
- Applicant Address: JP Osaka
- Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2015-087488 20150422
- Main IPC: H01L29/872
- IPC: H01L29/872 ; H01L29/16 ; H01L29/04 ; H01L29/66 ; H01L29/06 ; H01L29/36 ; H01L29/40

Abstract:
A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface, barrier regions having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier regions, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface, wherein each of the barrier regions has a polygonal boundary with the silicon carbide semiconductor layer, and each of sides of the polygonal boundary has an angle of 0° to 5° inclusive relative to direction of crystal orientations of the semiconductor substrate.
Public/Granted literature
- US20160315203A1 SEMICONDUCTOR DEVICE HAVING BARRIER REGION AND EDGE TERMINATION REGION ENCLOSING BARRIER REGION Public/Granted day:2016-10-27
Information query
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