公开(公告)号：USRE49195E1

公开(公告)日：2022-08-30

申请号：US16294567

申请日：2019-03-06

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Nobuyuki Horikawa ,  Osamu Kusumoto ,  Masashi Hayashi ,  Masao Uchida

IPC: H01L27/04 ,  H01L29/06 ,  H01L29/78 ,  H01L29/861 ,  H01L29/868 ,  H01L29/12 ,  H01L29/16 ,  H01L29/41 ,  H01L27/06 ,  H01L27/07 ,  H01L29/66 ,  H01L29/423 ,  H01L29/739

Abstract: A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.

公开(公告)号：US10229973B2

公开(公告)日：2019-03-12

申请号：US15477186

申请日：2017-04-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masao Uchida

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/16 ,  H01L21/02 ,  H01L29/66 ,  H01L29/73 ,  H01L31/02 ,  H01L29/872 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, having a first principal surface and a second principal surface, a silicon carbide semiconductor layer of the first conductivity type, disposed on the first principal surface, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the second principal surface and forming an ohmic junction with the semiconductor substrate. The semiconductor device satisfies 0.13≤Rc/Rd, where Rc is the contact resistance between the second principal surface and the second electrode at room temperature and Rd is the resistance of the silicon carbide semiconductor layer in a direction normal to the first principal surface at room temperature.

公开(公告)号：US09691759B2

公开(公告)日：2017-06-27

申请号：US15251886

申请日：2016-08-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masao Uchida ,  Nobuyuki Horikawa

IPC: H01L29/06 ,  H01L27/06 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/8213 ,  H01L27/0605 ,  H01L27/0727 ,  H01L29/1608 ,  H01L29/7827

Abstract: A semiconductor device includes a first silicon carbide semiconductor layer, a source including a source pad and a source wiring, a gate including a gate pad and a gate wiring, first unit cells disposed in a first element region, and second unit cells disposed in a second element region. In a plan view, the first and second element regions are adjacent to each other with the gate wiring between the first and second element regions. A first electrode including the gate electrode of each first unit cell is disposed in the first element region and electrically connected to the gate. A second electrode including the gate electrode of each second unit cell is disposed in the second element region and not electrically connected to the gate. The first and second electrodes are separated below the gate wiring.

公开(公告)号：US10224436B2

公开(公告)日：2019-03-05

申请号：US15944399

申请日：2018-04-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masao Uchida

IPC: H01L29/872 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, a silicon carbide semiconductor layer disposed on the semiconductor substrate, and a termination region disposed in the silicon carbide semiconductor layer. The termination region has a guard ring region and an FLR region which is disposed to surround the guard ring region while being separated from the guard ring region, the FLR region including a plurality of rings. The termination region includes a sector section, and in the sector section, an inner circumference and an outer circumference of at least one of the plurality of rings and an inner circumference and an outer circumference of the guard ring region have a same first center of curvature, the first center of curvature being positioned inside the inner circumference of the guard ring region, and a radius of curvature of the inner circumference of the guard ring region is 50 μm or less.

公开(公告)号：US09923090B2

公开(公告)日：2018-03-20

申请号：US15403381

申请日：2017-01-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Ohoka ,  Masao Uchida ,  Nobuyuki Horikawa ,  Osamu Kusumoto

IPC: H01L29/78 ,  H01L29/16 ,  H01L27/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/80

CPC classification number: H01L29/7803 ,  H01L21/28 ,  H01L27/0617 ,  H01L29/0696 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7828 ,  H01L29/80

Abstract: In the silicon carbide semiconductor element, a second silicon carbide semiconductor layer that is in contact with the surface of a first silicon carbide semiconductor layer has at least an upper layer including a dopant of a first conductivity type at a high concentration. Above a junction field effect transistor (JFET) region interposed between body regions that are disposed in the first silicon carbide semiconductor layer so as to be spaced from each other, the silicon carbide semiconductor element has a channel removed region, which is a cutout formed by removing a high concentration layer from the front surface side of the second silicon carbide semiconductor layer, the high concentration layer having a higher dopant concentration than at least the dopant concentration of the JFET region. The width of the channel removed region is smaller than that of the JFET region.

公开(公告)号：US09252211B2

公开(公告)日：2016-02-02

申请号：US14714226

申请日：2015-05-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masao Uchida ,  Osamu Kusumoto ,  Nobuyuki Horikawa

IPC: H01L29/15 ,  H01L29/745 ,  H01L21/00 ,  H01L21/338 ,  H01L29/06 ,  H01L27/06 ,  H01L29/872

CPC classification number: H01L29/0619 ,  H01L21/8213 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/0727 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/66068 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

Abstract: A semiconductor device includes a first silicon carbide semiconductor layer of a first conductive type that is positioned on a front surface of a substrate of the first conductive type, a transistor region that includes transistor cells, a Schottky region, and a boundary region. The boundary region includes a second body region and a gate connector that is arranged on the second body region via an insulating film and electrically connected with a gate electrode. The Schottky region includes a Schottky electrode that is arranged on the first silicon carbide semiconductor layer.

Abstract translation: 半导体器件包括位于第一导电类型的衬底的前表面上的第一导电类型的第一碳化硅半导体层，包括晶体管单元，肖特基区域和边界区域的晶体管区域。 边界区域包括第二体区域和栅极连接器，其经由绝缘膜布置在第二体区上并与栅电极电连接。 肖特基区域包括布置在第一碳化硅半导体层上的肖特基电极。

公开(公告)号：US11366022B2

公开(公告)日：2022-06-21

申请号：US16689135

申请日：2019-11-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Ohoka ,  Masahiko Niwayama ,  Masao Uchida

IPC: G01K7/01 ,  H01L27/02 ,  H01L29/16

Abstract: A semiconductor device is provided that includes a temperature sensing function that accurately senses a temperature. The semiconductor device includes a first semiconductor layer on a semiconductor substrate, and a temperature sensor. The temperature sensor includes: a sensing-body region of a second conductivity type that is disposed in the first semiconductor layer; a first region of a first conductivity type, and a second region of the first conductivity type that are arranged in the sensing-body region and are apart from each other; and a third region of the second conductivity type that is in the sensing-body region and is between the first region and the second region. A concentration of a first conductivity type impurity in the temperature-sensing conductive layer is higher than a concentration of a first conductivity type impurity in the drift region.

公开(公告)号：US10748838B2

公开(公告)日：2020-08-18

申请号：US16255874

申请日：2019-01-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Ohoka ,  Nobuyuki Horikawa ,  Masao Uchida

IPC: H01L23/482 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/417

Abstract: A silicon carbide semiconductor device includes an upper gate electrode including a gate pad and a gate wiring line, and an upper source electrode including first and second source pads. The gate wiring line includes a gate global wiring line extending to encircle the source pads, and a gate connection wiring line. The upper source electrode includes an outer periphery source wiring line extending to encircle the gate global wiring line, and first and second source connections connecting the outer periphery source wiring line to the first and second source pads, respectively. The gate global wiring line includes a first portion, a second portion, and a third portion. The first portion is split at a first substrate corner and a second substrate corner and lies between the first substrate corner and the second substrate corner.

公开(公告)号：US10361266B2

公开(公告)日：2019-07-23

申请号：US14726635

申请日：2015-06-01

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yuki Ueda ,  Masao Uchida

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/66 ,  H01L29/861 ,  H01L29/872 ,  H01L29/16

Abstract: A semiconductor device comprises a semiconductor substrate, a silicon carbide semiconductor layer of a first conductivity type on the semiconductor substrate, at least one ring-shaped region of a second conductivity type in the silicon carbide semiconductor layer, a first insulating film in contact with a part of the silicon carbide semiconductor layer, and a second insulating film which has a relative dielectric constant larger than a relative dielectric constant of the first insulating film and which is in contact with a part of the at least one ring-shaped region. In the semiconductor device, the at least one ring-shaped region is located in a termination region. The termination region surrounds a semiconductor element region when viewed from the direction perpendicular to a principal surface of the semiconductor substrate.

公开(公告)号：US10276470B2

公开(公告)日：2019-04-30

申请号：US15834035

申请日：2017-12-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masao Uchida

IPC: H01L23/00 ,  H01L23/31 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/739 ,  H01L29/872

Abstract: Semiconductor device 1000 includes semiconductor 102, an electric field relaxation structure, at least one surface electrode 112, passivation layer 114, and insulating layer 115. Semiconductor layer 102 has a predetermined element region. The electric field alleviation structure is disposed on semiconductor 102 at an end of the element region. On semiconductor 102, surface electrode 112 is disposed inside the electric field alleviation structure when viewed in a normal direction of semiconductor 102. Passivation layer 114 covers the electric field alleviation structure and a peripheral portion of at least one surface electrode 112, and has an opening portion above surface electrode 112. On surface electrode 112, insulating layer 115 is disposed inside opening portion 114p so as to be separated from passivation layer 114. When viewed in the normal direction of semiconductor 102, insulating layer 115 is disposed so as to surround partial region 112a of surface electrode 112.