Invention Grant
- Patent Title: Composite wafer semiconductor devices using offset via arrangements and methods of fabricating the same
-
Application No.: US15273029Application Date: 2016-09-22
-
Publication No.: US09780136B2Publication Date: 2017-10-03
- Inventor: Doowon Kwon
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Ward and Smith, P.A.
- Priority: KR10-2015-0135840 20150924
- Main IPC: H01L27/146
- IPC: H01L27/146 ; H04N5/225 ; H01L23/522 ; H01L23/00 ; H01L23/498 ; H01L25/065

Abstract:
A device includes a first integrated circuit substrate including a plurality of first metal layers interconnected by first vias and a second integrated circuit substrate on the first integrated circuit substrate and including second metal layers interconnected by second vias. An insulation layer is disposed between the first and second substrates and a connection region is disposed in the insulation layer and electrically connects a first one of the first metal layers to a first one of the second metal layers. The device further includes a bonding pad on the second substrate and a through via extending from the bonding pad and into the second to contact a second one of the second metal layers. The through via is positioned so as to not overlap at least one of the first vias, the second vias and the connection region. Methods of fabricating such device are also described.
Public/Granted literature
- US20170092680A1 COMPOSITE WAFER SEMICONDUCTOR DEVICES USING OFFSET VIA ARRANGEMENTS AND METHODS OF FABRICATING THE SAME Public/Granted day:2017-03-30
Information query
IPC分类: