Invention Grant
- Patent Title: Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing
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Application No.: US15182527Application Date: 2016-06-14
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Publication No.: US09793279B2Publication Date: 2017-10-17
- Inventor: Jeng-Wei Yang , Man-Tang Wu , Chun-Ming Chen , Mandana Tadayoni , Chien-Sheng Su , Nhan Do
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L27/11524 ; H01L29/423 ; H01L21/28 ; H01L29/788 ; H01L29/66 ; G11C16/26 ; H01L27/11521

Abstract:
A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate.
Public/Granted literature
Information query
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