Invention Grant
- Patent Title: Methods of design rule checking of circuit designs
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Application No.: US15040235Application Date: 2016-02-10
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Publication No.: US09798852B2Publication Date: 2017-10-24
- Inventor: Lei Yuan , Jongwook Kye , Harry J. Levinson
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L21/027

Abstract:
Methods for performing design rule checking of a circuit design are provided. The methods include, for instance: providing a circuit design for an integrated circuit layer, in which the circuit design includes a plurality of design lines oriented in a particular direction; and automatically performing a design rule check of the circuit design, which may include forming a verification pattern for the circuit design, the verification pattern comprising a plurality of verification lines and a plurality of verification regions, wherein one or more verification regions are associated with and connected to one verification line of the plurality of verification lines, and checking the verification pattern for any verification line overlapping a verification region. The circuit design may be considered to fail the design rule check if an end of one verification line overlaps any verification region associated with another verification line of the verification pattern.
Public/Granted literature
- US20160378906A1 METHODS OF DESIGN RULE CHECKING OF CIRCUIT DESIGNS Public/Granted day:2016-12-29
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