Display panel including buffer circuit to compensate for RC delay of a clock signal
Abstract:
A display panel includes a plurality of pixels, a gate driver, a clock pad, and a buffer circuit. The gate driver supplies gate signals to the plurality of pixels. The clock pad receives a clock signal. The buffer circuit is connected between the clock pad and the gate driver. The buffer circuit compensates for an RC delay of the clock signal received through the clock pad, and supplies the clock signal of which the RC delay is compensated to the gate driver.
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