Invention Grant
- Patent Title: Semiconductor device
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Application No.: US14403225Application Date: 2014-01-27
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Publication No.: US09806147B2Publication Date: 2017-10-31
- Inventor: Kosuke Yoshida , Tetsuya Nitta , Atsushi Sakai
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- International Application: PCT/JP2014/051674 WO 20140127
- International Announcement: WO2015/111218 WO 20150730
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/78 ; H01L29/10 ; H01L29/739
Abstract:
In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.
Public/Granted literature
- US20160181357A1 SEMICONDUCTOR DEVICE Public/Granted day:2016-06-23
Information query
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