公开(公告)号：US09583604B2

公开(公告)日：2017-02-28

申请号：US14500324

申请日：2014-09-29

Applicant: Renesas Electronics Corporation

Inventor： Mikio Tsujiuchi ,  Tetsuya Nitta

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7393 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/7395

Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.

Abstract translation: 可以抑制在整体电流能力下降的同时提高短路能力的半导体装置。 在半导体装置中，在半导体衬底的主表面上沿一个方向排列成一行的多个IGBT（绝缘栅双极型晶体管）包括位于一个方向上的末端的IGBT， IGBT位于极端。 位于极端的IGBT的电流能力高于位于中心位置的IGBT的电流能力。

公开(公告)号：US20160181357A1

公开(公告)日：2016-06-23

申请号：US14403225

申请日：2014-01-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kosuke Yoshida ,  Tetsuya Nitta ,  Atsushi Sakai

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/7393 ,  H01L29/7813 ,  H01L29/7816

Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (Si) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.

Abstract translation: 在半导体装置中，在n +源极区域（SR）的第一和第二部分（P1，P2）之间的主表面（Si）中布置有p +背栅极区域（PBG），并且配置在靠近n + 漏极区域（DR）相对于n +源极区域（SR）。 由此，可以获得具有高导通状态击穿电压的半导体器件。

公开(公告)号：US09972679B2

公开(公告)日：2018-05-15

申请号：US14620401

申请日：2015-02-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hajime Kataoka ,  Tatsuya Shiromoto ,  Tetsuya Nitta

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/78 ,  H01L21/761 ,  H01L21/764 ,  H01L21/76 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L23/31 ,  H01L23/485 ,  H01L23/522

CPC classification number: H01L29/0653 ,  H01L21/761 ,  H01L21/764 ,  H01L23/3171 ,  H01L23/485 ,  H01L23/522 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To provide a semiconductor device having improved performances. A semiconductor substrate has, in the surface layer portion thereof, an n+ type semiconductor region for source and an n+ type semiconductor region for drain separated from each other. The semiconductor substrate has, on the main surface thereof between the n+ type semiconductor region for source and the n+ type semiconductor region for drain, a gate electrode via an insulating film as a gate insulating film. The semiconductor substrate has, in the main surface thereof between the channel formation region below the gate electrode and the n+ type semiconductor region for drain, a LOCOS oxide film and an STI insulating. Of the LOCOS oxide film and the STI insulating film, the LOCOS oxide film is located on the side of the channel formation region and the STI insulating film is on the side of the n+ type semiconductor region DR for drain.

公开(公告)号：USRE46773E1

公开(公告)日：2018-04-03

申请号：US15093108

申请日：2016-04-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuma Onishi ,  Yoshitaka Otsu ,  Hiroshi Kimura ,  Tetsuya Nitta ,  Shinichiro Yanagi ,  Katsumi Morii

IPC: H01L29/00 ,  H01L29/06 ,  H01L27/092 ,  H01L27/11521 ,  H01L27/11526 ,  H01L21/764 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

公开(公告)号：US09881868B2

公开(公告)日：2018-01-30

申请号：US14516806

申请日：2014-10-17

Applicant: Renesas Electronics Corporation

Inventor： Shigeo Tokumitsu ,  Takahiro Mori ,  Tetsuya Nitta

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/08 ,  H01L23/532

CPC classification number: H01L23/5228 ,  H01L23/53223 ,  H01L23/53266 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554

Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.

公开(公告)号：USRE48450E1

公开(公告)日：2021-02-23

申请号：US15919925

申请日：2018-03-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuma Onishi ,  Yoshitaka Otsu ,  Hiroshi Kimura ,  Tetsuya Nitta ,  Shinichiro Yanagi ,  Katsumi Morii

IPC: H01L29/06 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/10 ,  H01L29/08 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

公开(公告)号：US10249708B2

公开(公告)日：2019-04-02

申请号：US15727400

申请日：2017-10-06

Applicant: Renesas Electronics Corporation

Inventor： Kosuke Yoshida ,  Tetsuya Nitta ,  Atsushi Sakai

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/739

Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.

公开(公告)号：US10128359B2

公开(公告)日：2018-11-13

申请号：US15405725

申请日：2017-01-13

Applicant: Renesas Electronics Corporation

Inventor： Mikio Tsujiuchi ,  Tetsuya Nitta

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10

Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.

公开(公告)号：US20180033855A1

公开(公告)日：2018-02-01

申请号：US15727400

申请日：2017-10-06

Applicant: Renesas Electronics Corporation

Inventor： Kosuke Yoshida ,  Tetsuya Nitta ,  Atsushi Sakai

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7393 ,  H01L29/7813 ,  H01L29/7816

Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.

公开(公告)号：US09806147B2

公开(公告)日：2017-10-31

申请号：US14403225

申请日：2014-01-27

Applicant: Renesas Electronics Corporation

Inventor： Kosuke Yoshida ,  Tetsuya Nitta ,  Atsushi Sakai

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/739

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/7393 ,  H01L29/7813 ,  H01L29/7816

Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.