- 专利标题: Methods and systems for reducing electrical disturb effects between thyristor memory cells using buried metal cathode lines
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申请号: US15199934申请日: 2016-06-30
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公开(公告)号: US09812454B2公开(公告)日: 2017-11-07
- 发明人: Harry Luan , Valery Axelrad , Charlie Cheng
- 申请人: Kilopass Technology, Inc.
- 申请人地址: US CA San Jose
- 专利权人: Kilopass Technology, Inc.
- 当前专利权人: Kilopass Technology, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Aka Chan LLP
- 主分类号: H01L29/74
- IPC分类号: H01L29/74 ; H01L27/102 ; H01L23/532 ; H01L29/45 ; H01L21/8229 ; H01L21/285
摘要:
Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.