公开(公告)号：US09899390B2

公开(公告)日：2018-02-20

申请号：US15199916

申请日：2016-06-30

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： H01L29/74 ,  H01L27/102 ,  H01L21/285 ,  H01L21/8229 ,  H01L23/532 ,  H01L29/45 ,  H01L21/02 ,  H01L21/22 ,  H01L21/3205 ,  H01L27/108 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L21/265 ,  H01L29/161 ,  G11C11/39 ,  H01L27/08 ,  H01L29/08

CPC分类号： H01L27/1027 ,  G11C11/39 ,  H01L21/02271 ,  H01L21/221 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/32053 ,  H01L21/8229 ,  H01L23/53209 ,  H01L23/53242 ,  H01L27/0817 ,  H01L27/1023 ,  H01L27/10802 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0839 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66363 ,  H01L29/74 ,  H01L29/87

摘要： Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.

公开(公告)号：US20170372766A1

公开(公告)日：2017-12-28

申请号：US15426909

申请日：2017-02-07

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： G11C11/39 ,  H01L29/74 ,  H01L27/102

CPC分类号： G11C11/39 ,  H01L27/1027 ,  H01L29/74 ,  H01L29/749

摘要： A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.

公开(公告)号：US20170229464A1

公开(公告)日：2017-08-10

申请号：US15199916

申请日：2016-06-30

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： H01L27/102 ,  H01L21/265 ,  H01L29/161 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L27/1027 ,  G11C11/39 ,  H01L21/02271 ,  H01L21/221 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/32053 ,  H01L21/8229 ,  H01L23/53209 ,  H01L23/53242 ,  H01L27/0817 ,  H01L27/1023 ,  H01L27/10802 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0839 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66363 ,  H01L29/74 ,  H01L29/87

摘要： Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.

公开(公告)号：US09564198B2

公开(公告)日：2017-02-07

申请号：US14740197

申请日：2015-06-15

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC分类号： H01L27/06 ,  H01L21/8249 ,  G11C11/39 ,  G11C11/411 ,  G11C11/419 ,  H01L27/102 ,  H01L27/11 ,  G11C11/416

CPC分类号： H01L27/0623 ,  G11C11/39 ,  G11C11/4113 ,  G11C11/4116 ,  G11C11/416 ,  G11C11/419 ,  H01L21/8249 ,  H01L27/1025 ,  H01L27/1027 ,  H01L27/11 ,  H01L29/7404 ,  H01L29/7436

摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

摘要翻译： 描述了基于用于SRAM集成电路的晶闸管的双晶体管存储单元及其制造方法。 存储器单元可以在具有浅沟槽隔离的半导体衬底中的晶闸管的MOS和双极选择晶体管的不同组合中实现，或者不具有选择晶体管。 标准CMOS工艺技术可用于制造SRAM。

公开(公告)号：US20170025414A1

公开(公告)日：2017-01-26

申请号：US15283085

申请日：2016-09-30

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： H01L27/102 ,  H01L21/762 ,  H01L29/45 ,  G11C11/39 ,  H01L21/321 ,  H01L29/06 ,  H01L29/10 ,  H01L29/749 ,  H01L29/66 ,  H01L21/28

CPC分类号： H01L27/1027 ,  G11C11/39 ,  H01L21/28035 ,  H01L21/321 ,  H01L21/324 ,  H01L21/76224 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/1016 ,  H01L29/102 ,  H01L29/16 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/749

摘要： A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.

摘要翻译： 公开了使用垂直晶闸管的易失性存储器阵列以及制造阵列的方法。

公开(公告)号：US20160379984A1

公开(公告)日：2016-12-29

申请号：US15197640

申请日：2016-06-29

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： H01L27/102 ,  G11C11/406 ,  H01L29/06

CPC分类号： H01L27/1027 ,  G11C11/4026 ,  G11C11/40622 ,  G11C2211/4068 ,  H01L27/1023 ,  H01L29/0649 ,  H01L29/749

摘要： A volatile memory array using vertical thyristors with gates, NMOS or PMOS, in trenches adjacent the thyristors is disclosed together with methods of fabricating the array.

摘要翻译： 在与晶闸管相邻的沟槽中使用具有栅极，NMOS或PMOS的垂直晶闸管的易失性存储器阵列与制造阵列的方法一起公开。

公开(公告)号：US20160379720A1

公开(公告)日：2016-12-29

申请号：US15154911

申请日：2016-05-13

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Tao Su ,  Steve Wang ,  Charlie Cheng

IPC分类号： G11C17/18 ,  G11C17/16

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A method of programming one-time programmable (OTP) memory cells in an array is described. Each memory cell has a MOSFET programming element and a MOSFET pass transistor, the MOSFET pass transistor having a gate electrode over a channel region between two source/drain regions, and the MOSFET programming element having a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor. The other source/drain region of the MOSFET pass transistor is coupled to a bit line. The memory cell is programmed by setting a first voltage of a first polarity on the gate electrode of the pass transistor to electrically connect the source/drain regions of the pass transistor; setting a second voltage of the first polarity on the gate electrode of the programming element; and setting a third voltage of a second polarity on the bit line. The voltage across an oxide layer between the gate electrode and channel region of the programming element ruptures the oxide layer and effectively programs the programming element.

摘要翻译： 描述了在阵列中编程一次性可编程（OTP）存储器单元的方法。 每个存储单元具有MOSFET编程元件和MOSFET通过晶体管，MOSFET通过晶体管在两个源极/漏极区域之间的沟道区域上具有栅电极，并且MOSFET编程元件在与源极相邻的沟道区域上具有栅电极 /漏极区域是与MOSFET通过晶体管相关联的两个源极/漏极中的一个的一部分或与其连接的漏极区域。 MOSFET通过晶体管的另一个源极/漏极区域耦合到位线。 通过在传输晶体管的栅电极上设置第一极性的第一电压来对存储单元进行编程，以电连接传输晶体管的源极/漏极区; 在编程元件的栅电极上设置第一极性的第二电压; 并在位线上设置第二极性的第三电压。 编程元件的栅电极和沟道区之间的氧化层两端的电压使氧化层破裂并有效地编程编程元件。

公开(公告)号：US09449669B2

公开(公告)日：2016-09-20

申请号：US14590834

申请日：2015-01-06

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC分类号： G11C11/39 ,  G11C11/411 ,  G11C11/419 ,  H01L21/8249 ,  H01L27/06 ,  G11C11/416

CPC分类号： H01L27/0623 ,  G11C11/39 ,  G11C11/4113 ,  G11C11/4116 ,  G11C11/416 ,  G11C11/419 ,  H01L21/8249 ,  H01L27/1025 ,  H01L27/1027 ,  H01L27/11 ,  H01L29/7404 ,  H01L29/7436

摘要： A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells. Special circuitry provides lowered power consumption during standby.

摘要翻译： 基于用于SRAM集成电路的晶闸管的存储单元可以在具有浅沟槽隔离的半导体衬底中的晶闸管的MOS和双极选择晶体管的不同组合中实现，或者不具有选择晶体管。 标准CMOS工艺技术可用于制造SRAM单元。 特殊电路在待机期间提供降低的功耗。

公开(公告)号：US20160093357A1

公开(公告)日：2016-03-31

申请号：US14841578

申请日：2015-08-31

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： G11C11/39

CPC分类号： G11C11/39 ,  G11C11/401 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4096 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/76224 ,  H01L27/1027 ,  H01L29/0649 ,  H01L29/66363 ,  H01L29/74

摘要： A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.

摘要翻译： 公开了使用垂直晶闸管的易失性存储器阵列以及操作阵列以读取，写入，保留和刷新存储在其中的数据的方法。

公开(公告)号：US10535657B2

公开(公告)日：2020-01-14

申请号：US15683760

申请日：2017-08-22

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Valery Axelrad

IPC分类号： H01L27/102 ,  H01L21/8229 ,  H01L27/108 ,  H01L27/11512 ,  G11C15/04 ,  H01L29/66 ,  G11C11/39 ,  H01L27/08

摘要： Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.