Invention Grant
- Patent Title: Dynamic subroutine linkage optimizing shader performance
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Application No.: US15208328Application Date: 2016-07-12
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Publication No.: US09824484B2Publication Date: 2017-11-21
- Inventor: Michael V. Oneppo , Craig Peeper , Andrew L. Bliss , John L. Rapp , Mark M. Lacey
- Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
- Applicant Address: US WA Redmond
- Assignee: Microsoft Technology Licensing, LLC
- Current Assignee: Microsoft Technology Licensing, LLC
- Current Assignee Address: US WA Redmond
- Agency: Shook, Hardy & Bacon L.L.P.
- Main IPC: G06T15/50
- IPC: G06T15/50 ; G06T15/00 ; G06F9/45 ; G06F9/44 ; G06T15/80 ; G06F9/54 ; G06T1/20

Abstract:
Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more registers. To do so, developers' high level shading level (HLSL) language includes template classes of shaders that can later be replaced by complex or simple versions of the shader. The HLSL is converted to bytecode that can be used to rasterize pixels on a computing device.
Public/Granted literature
- US20170039754A1 DYNAMIC SUBROUTINE LINKAGE OPTIMIZING SHADER PERFORMANCE Public/Granted day:2017-02-09
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |
G06T15/50 | .发光效果 |