Invention Grant
- Patent Title: High throughput VLSI architecture for HEVC SAO encoding
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Application No.: US14320712Application Date: 2014-07-01
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Publication No.: US09826240B2Publication Date: 2017-11-21
- Inventor: Mihir Narendra Mody , Hrushikesh Tukaram Garud , Soyeb Nagori
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Charles A. Brill; Frank D. Cimino
- Priority: IN3014/CHE/2013 20130705
- Main IPC: H04N19/117
- IPC: H04N19/117 ; H04N19/119 ; H04N19/89 ; H04N19/44 ; H04N19/80 ; H04N19/132 ; H04N19/176 ; H04N19/14 ; H04N19/82

Abstract:
An apparatus for sample adaptive offset (SAO) filtering in video encoding. A unified processing engine collects statistics on a block of pixels, determines a minimum RD cost (J) for each category of band offsets and edge offsets; determines a RD cost to find the optimal SAO type and determines a cost for each of the left SAO parameters and the up SAO parameters. The unified processing engine operates for three iterations: once for luminance once for each chrominance. A SAO merge decision unit determines an optimal mode and generates current LCU Parameters. The RD offset unit determination includes determining whether the sign of the minimum offset is proper for the category of edge offset. The RD offset is determined using a programmable look-up table indexed by the offset to estimate a rate. The unified processing engine operates on a three stage pipeline: loading blocks; processing; and updating blocks.
Public/Granted literature
- US20150010052A1 High Throughput VLSI Architecture for HEVC SAO Encoding Public/Granted day:2015-01-08
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