- 专利标题: Enhanced board level reliability for wafer level packages
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申请号: US14496049申请日: 2014-09-25
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公开(公告)号: US09837368B2公开(公告)日: 2017-12-05
- 发明人: Peter R. Harper , Martin Mason , Arkadii V. Samoilov
- 申请人: Maxim Integrated Products, Inc.
- 申请人地址: US CA San Jose
- 专利权人: Maxim Integrated Products, Inc.
- 当前专利权人: Maxim Integrated Products, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Advent, LLP
- 主分类号: H01L23/00
- IPC分类号: H01L23/00 ; H01L23/31 ; H01L21/56
摘要:
A wafer level package device, electronic device, and fabrication methods for fabrication of the wafer level package device are described that include forming an exposed lead tip on the wafer level package for providing a solder buttress structure when coupling the wafer level package device to another electrical component. In implementations, the wafer level package device includes at least one integrated circuit die, a metal pad, a first dielectric layer, a redistribution layer, a second dielectric layer, a pillar structure, a molding layer, a pillar layer, and a plating layer, where the pillar layer is sawn to form pad contacts on at least two sides of the wafer level package device. The exposed pad contact facilitate a solder fillet and buttress structure resulting in improved board level reliability.
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