利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

41 条记录 (耗时 0.02 秒)

    MEMS-BASED WAFER LEVEL PACKAGING FOR THERMO-ELECTRIC IR DETECTORS
    1.
    发明申请
    MEMS-BASED WAFER LEVEL PACKAGING FOR THERMO-ELECTRIC IR DETECTORS 审中-公开
    用于热电红外探测器的基于MEMS的水平包装

    公开(公告)号：US20160163942A1

    公开(公告)日：2016-06-09

    申请号：US14958552

    申请日：2015-12-03

    申请人： Maxim Integrated Products, Inc.

    发明人： Arvin Emadi ,  Nicole D. Kerness ,  Arkadii V. Samoilov ,  Abhishek Sahasrabudhe

    IPC分类号： H01L35/02 ,  H01L35/20 ,  H01L35/14

    CPC分类号： H01L35/02 ,  G01J5/0225 ,  G01J5/024 ,  G01J5/12 ,  H01L27/14649 ,  H01L35/14 ,  H01L35/20

    摘要： A device and techniques for fabricating the device are described for forming a wafer-level thermal sensor package using microelectromechanical system (MEMS) processes. In one or more implementations, a wafer level thermal sensor package includes a thermopile stack, which includes a substrate, a dielectric membrane, a first thermoelectric layer, a first interlayer dielectric, a second thermoelectric layer, a second interlayer dielectric, a metal connection assembly, a passivation layer, where the passivation layer includes at least one of a trench or a hole, and where the substrate includes a cavity adjacent to the at least one trench or hole, and a bond pad disposed on the passivation layer and electrically coupled to the metal connection assembly; and a cap wafer assembly coupled to the thermopile stack, the cap wafer assembly including a wafer having a cavity formed on a side of the wafer configured to be adjacent to the thermopile stack.

    摘要翻译： 描述了用于制造该器件的器件和技术，用于使用微机电系统（MEMS）工艺形成晶片级热传感器封装。 在一个或多个实施方案中，晶片级热传感器封装包括热电堆，其包括基板，介电膜，第一热电层，第一层间电介质，第二热电层，第二层间电介质，金属连接组件 钝化层，其中所述钝化层包括沟槽或孔中的至少一个，并且其中所述衬底包括与所述至少一个沟槽或孔相邻的空腔，以及设置在所述钝化层上并且电耦合到 金属连接组件; 以及联接到所述热电堆叠的盖晶片组件，所述盖晶片组件包括晶片，所述晶片具有形成在所述晶片的一侧上的空腔，所述晶片被配置为与所述热堆叠相邻。

    ULTRAVIOLET SENSOR HAVING FILTER
    2.
    发明申请
    ULTRAVIOLET SENSOR HAVING FILTER 审中-公开
    ULTRAVIOLET传感器有过滤器

    公开(公告)号：US20150338273A1

    公开(公告)日：2015-11-26

    申请号：US14580406

    申请日：2014-12-23

    申请人： Maxim Integrated Products, Inc.

    发明人： Arvin Emadi ,  Nicole D. Kerness ,  Cheng-Wei Pei ,  Joy T. Jones ,  Arkadii V. Samoilov ,  Ke-Cai Zeng

    IPC分类号： G01J1/42 ,  G01J1/04 ,  G01J3/02

    CPC分类号： G01J1/429 ,  G01J1/0488 ,  H01L31/02162 ,  H01L31/101

    摘要： Techniques are provided to furnish a light sensor that includes a filter positioned over a photodetector to filter visible and infrared wavelengths to permit the sensing of ultraviolet (UV) wavelengths. In one or more implementations, the light sensor comprises a semiconductor device (e.g., a die) that includes a substrate. A photodetector (e.g., photodiode, phototransistor, etc.) is formed in the substrate proximate to the surface of the substrate. In one or more implementations, the substrate comprises a silicon on insulator substrate (SOI). A filter (e.g., absorption filter, interference filter, flat pass filter, McKinlay-Diffey Erythema Action Spectrum-based filter, UVA/UVB filter, and so forth) is disposed over the photodetector. The filter is configured to filter infrared light and visible light from light received by the light sensor to at least substantially block infrared light and visible light from reaching the photodetector. The thickness of the SOI substrate can be tailored to modify received UV/visible wavelength ratios.

    摘要翻译： 提供技术来提供光传感器，其包括位于光电检测器上方的过滤器，以过滤可见光和红外波长以允许感测紫外（UV）波长。 在一个或多个实施方式中，光传感器包括包括衬底的半导体器件（例如裸片）。 光电探测器（例如，光电二极管，光电晶体管等）形成在靠近衬底表面的衬底中。 在一个或多个实施方案中，衬底包括绝缘体上硅衬底（SOI）。 滤光器（例如，吸收滤光器，干涉滤光器，平通滤光片，McKinlay-Diffey Erythema Action Spectrum滤光片，UVA / UVB滤光片等）设置在光电探测器上。 过滤器被配置为从由光传感器接收的光中过滤红外光和可见光，以至少基本上阻挡红外光和可见光到达光电检测器。 可以调整SOI衬底的厚度以修改接收的UV /可见波长比。

    FAN-OUT AND HETEROGENEOUS PACKAGING OF ELECTRONIC COMPONENTS
    4.
    发明申请
    FAN-OUT AND HETEROGENEOUS PACKAGING OF ELECTRONIC COMPONENTS 有权
    电子元件的扇出和异质包装

    公开(公告)号：US20140252655A1

    公开(公告)日：2014-09-11

    申请号：US13930141

    申请日：2013-06-28

    申请人： Maxim Integrated Products, Inc.

    发明人： Khanh Tran ,  Arkadii V. Samoilov ,  Pirooz Parvarandeh ,  Amit S. Kelkar

    IPC分类号： H01L23/538

    CPC分类号： H01L23/5389 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/147 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/157

    摘要： Aspects of the disclosure pertain to a packaging structure configured for providing heterogeneous packaging of electronic components and a process for making same. The packaging structure includes a carrier substrate having a plurality of cavities formed therein. The packaging structure further includes a first die and a second die. The first die is at least substantially contained within a first cavity included in the plurality of cavities. The second die is at least substantially contained within a second cavity included in the plurality of cavities. The first die is fabricated via a first fabrication technology, and the second die is fabricated via a second fabrication technology, the second fabrication technology being different than the first fabrication technology. The packaging structure also includes electrical interconnect circuitry connected to (e.g., for electrically connecting) the first die, the second die and/or the carrier substrate.

    摘要翻译： 本公开的方面涉及被配置为提供电子部件的异质包装的包装结构和用于制造其的方法。 包装结构包括其中形成有多个空腔的载体基板。 包装结构还包括第一模具和第二模具。 第一模具至少基本上包含在包括在多个空腔中的第一空腔内。 第二模具至少基本上包含在包括在多个空腔中的第二空腔内。 第一个模具通过第一制造技术制造，并且第二个模具通过第二制造技术制造，第二制造技术不同于第一制造技术。 封装结构还包括连接到（例如，用于电连接）第一管芯，第二管芯和/或载体衬底的电互连电路。

    MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE
    5.
    发明申请
    MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE 有权
    多芯片，高电流等级封装

    公开(公告)号：US20140183747A1

    公开(公告)日：2014-07-03

    申请号：US13732664

    申请日：2013-01-02

    申请人： Maxim Integrated Products, Inc.

    发明人： Arkadii V. Samoilov ,  Peter R. Harper ,  Viren Khandekar ,  Pirooz Parvarandeh

    IPC分类号： H01L23/28 ,  H01L21/56

    CPC分类号： H01L23/49838 ,  H01L21/311 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/563 ,  H01L23/28 ,  H01L23/3107 ,  H01L24/81 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/00 ,  H01L2224/03

    摘要： Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts.

    摘要翻译： 描述了用于高电流应用的晶片级封装半导体器件，其具有用于提供电互连性的柱。 在一个实现中，晶片级封装器件包括集成电路芯片，其具有形成在集成电路芯片上的至少一个柱。 支柱被配置为提供与集成电路芯片的电互连性。 晶片级封装器件还包括被配置为支撑柱的封装结构。 晶片级封装器件还包括在集成电路芯片（例如，大裸片）上配置的集成电路芯片器件（例如，小芯片）。 在晶片级封装器件中，集成电路芯片器件的高度小于柱的高度和/或小于柱和一个或多个焊接触点的组合高度。