- 专利标题: Method and system for advanced fail data transfer mechanisms
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申请号: US14701345申请日: 2015-04-30
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公开(公告)号: US09842038B2公开(公告)日: 2017-12-12
- 发明人: Xinguo Zhang , Yi Liu , Ze'ev Raz , Darrin Albers , Alan S. Krech, Jr. , Shigeo Chiyoda , Jesse Hobbs
- 申请人: Advantest Corporation
- 申请人地址: JP Tokyo
- 专利权人: Advantest Corporation
- 当前专利权人: Advantest Corporation
- 当前专利权人地址: JP Tokyo
- 主分类号: G06F11/273
- IPC分类号: G06F11/273 ; G06F11/22 ; G06F11/07
摘要:
Embodiments of the present invention utilize a dual buffer size threshold system for raising interrupts that allows DUT testing systems to perform real-time buffer memory allocation procedures in an on demand basis. Using dual interrupt threshold systems in the manner described by embodiments of the present invention, DUT testing systems can reduce the need to decide on a single buffer size threshold when testing a set of DUTs that separately provide different amounts of fail data relative to each other. As such, embodiments of the present invention can minimize the overhead processing spent on interrupt handling while also reducing the amount wait time needed for the data processing module to process fail data for each DUT. Thus, embodiments of the present invention can increase the use of tester resources more efficiently while decrease the amount of time a tester system spends collecting and/or analyzing fail data for a set of DUTs during a testing session.
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