- 专利标题: Apparatus and method for hardware-accelerated packet processing
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申请号: US14750085申请日: 2015-06-25
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公开(公告)号: US09847936B2公开(公告)日: 2017-12-19
- 发明人: Nrupal Jani , Dinesh Kumar , Christian Maciocco , Ren Wang , Neerav Parikh , John Fastabend , Iosif Gasparakis , David J. Harriman , Patrick L. Connor , Sanjeev Jain
- 申请人: Nrupal Jani , Dinesh Kumar , Christian Maciocco , Ren Wang , Neerav Parikh , John Fastabend , Iosif Gasparakis , David J. Harriman , Patrick L. Connor , Sanjeev Jain
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwegman Lundberg & Woessner, P.A.
- 主分类号: H04L12/721
- IPC分类号: H04L12/721 ; H04L12/26 ; H04L12/725 ; H04L12/803 ; H04L12/911
摘要:
Devices and techniques for hardware accelerated packet processing are described herein. A device can communicate with one or more hardware switches. The device can detect characteristics of a plurality of packet streams. The device may distribute the plurality of packet streams between the one or more hardware switches and software data plane components based on the detected characteristics of the plurality of packet streams, such that at least one packet stream is designated to be processed by the one or more hardware switches. Other embodiments are also described.