Invention Grant
- Patent Title: Techniques for scalable endpoint addressing for parallel applications
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Application No.: US14998255Application Date: 2015-12-24
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Publication No.: US09852107B2Publication Date: 2017-12-26
- Inventor: Keith Underwood , Charles F. Giefer , David Addison
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Grossman, Tucker, Perreault & Pfleger, PLLC
- Main IPC: G06F15/173
- IPC: G06F15/173 ; G06F9/48 ; G06F3/06

Abstract:
Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node. The node may then execute an operation in accordance with the inter-process communication, such as a get or set against a memory associated with the node.
Public/Granted literature
- US20170185563A1 Techniques for scalable endpoint addressing for parallel applications Public/Granted day:2017-06-29
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