公开(公告)号：US09852107B2

公开(公告)日：2017-12-26

申请号：US14998255

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Keith Underwood ,  Charles F. Giefer ,  David Addison

IPC: G06F15/173 ,  G06F9/48 ,  G06F3/06

CPC classification number: G06F15/17331 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G06F9/4881 ,  G06F9/547 ,  G06F12/00 ,  G06F13/00 ,  H04L67/10

Abstract: Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node. The node may then execute an operation in accordance with the inter-process communication, such as a get or set against a memory associated with the node.

公开(公告)号：US20170185563A1

公开(公告)日：2017-06-29

申请号：US14998255

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Keith Underwood ,  Charles F. Giefer ,  David Addison

IPC: G06F15/173 ,  G06F9/48 ,  G06F3/06

CPC classification number: G06F15/17331 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G06F9/4881 ,  G06F9/547 ,  G06F12/00 ,  G06F13/00 ,  H04L67/10

Abstract: Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node. The node may then execute an operation in accordance with the inter-process communication, such as a get or set against a memory associated with the node.