Invention Grant
- Patent Title: System and method in indium-gallium-arsenide channel height control for sub 7nm FinFET
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Application No.: US15416287Application Date: 2017-01-26
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Publication No.: US09852903B2Publication Date: 2017-12-26
- Inventor: Chun Yan , Xinyu Bao
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED MATERIALS, INC.
- Current Assignee: APPLIED MATERIALS, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/66 ; H01L21/3105

Abstract:
A method for forming a group III-V semiconductor channel region in a transistor is provided herein. The method includes exposing a substrate including an oxide layer to a first plasma to treat the oxide layer, exposing the treated oxide layer to a second plasma to convert the oxide layer to an evaporable layer, evaporating the evaporable layer to expose a group III-V semiconductor material surface, and exposing the group III-V semiconductor material surface to an oxygen containing gas to oxidize the group III-V semiconductor material. The processes may be repeated until a recessed depth having a predetermined depth is formed. A group III-V semiconductor channel is then formed in the predetermined recessed depth. The control of the height of the group III-V semiconductor channel is improved.
Public/Granted literature
- US20170221706A1 SYSTEM AND METHOD IN INDIUM-GALLIUM-ARSENIDE CHANNEL HEIGHT CONTROL FOR SUB 7NM FINFET Public/Granted day:2017-08-03
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