Invention Grant
- Patent Title: Warpage reduction in structures with electrical circuitry
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Application No.: US15181861Application Date: 2016-06-14
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Publication No.: US09853000B2Publication Date: 2017-12-26
- Inventor: Cyprian Emeka Uzoh
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/30 ; H01L23/00 ; H01L21/3205 ; H01L21/78 ; H01L21/66

Abstract:
To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-balancing. For example, the stress/management layer can be debonded from the wafer at selected locations, or recesses can be formed in the layer, or phase changes can be induced in the layer. In other embodiments, this layer is tantalum-aluminum that may or may not over-balance the warpage; this layer is believed to reduce warpage due to crystal-phase-dependent stresses which dynamically adjust to temperature changes so as to reduce the warpage (possibly keeping the wafer flat through thermal cycling). Other features are also provided.
Public/Granted literature
- US20160293556A1 WARPAGE REDUCTION IN STRUCTURES WITH ELECTRICAL CIRCUITRY Public/Granted day:2016-10-06
Information query
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