- Patent Title: Method for automatically generating a netlist of an FPGA program
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Application No.: US14711116Application Date: 2015-05-13
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Publication No.: US09870440B2Publication Date: 2018-01-16
- Inventor: Heiko Kalte , Dominik Lubeley
- Applicant: dSPACE digital signal processing and control engineering GmbH
- Applicant Address: DE Paderborn
- Assignee: dSPACE digital signal processing and control engineering GmbH
- Current Assignee: dSPACE digital signal processing and control engineering GmbH
- Current Assignee Address: DE Paderborn
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Priority: EP14168015 20140513; EP15165320 20150428
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method for generating a netlist of an FPGA program. The model of the FPGA program is composed of at least two components, each component being assigned a separate partition on the FPGA. An independent build is carried out for each component and an overall classification is generated from the components, wherein the build jobs are automatically started after a trigger event and the trigger event is a saving of a component, the exiting of a component of the design, or a time-controlled, automated initiation of a build.
Public/Granted literature
- US20150331983A1 METHOD FOR AUTOMATICALLY GENERATING A NETLIST OF AN FPGA PROGRAM Public/Granted day:2015-11-19
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