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公开(公告)号：US11442884B2
公开(公告)日：2022-09-13
申请号：US17215967
申请日：2021-03-29
Inventor： Andreas Agne , Dominik Lubeley , Heiko Kalte , Marc Schlenger
IPC: G06F13/42
Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.
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公开(公告)号：US09628085B1
公开(公告)日：2017-04-18
申请号：US15334659
申请日：2016-10-26
Inventor： Heiko Kalte , Dominik Lubeley , Lukas Funke
IPC: G11C7/10 , H03K19/177 , G11C7/22
CPC classification number: H03K19/1776 , G11C7/10 , G11C7/222 , H03K19/17776
Abstract: A method for accessing signals of a programmable logic device having a functional level and a configuration level at run time when the programmable logic device is executing a predefined configuration. An access to at least one signal value that has a number of bits is requested. The individual bits in the configuration are each located in an address unit with one address offset apiece such that one or more bits of a signal value are located in one address unit. A bitwise access to the requested signal values takes place, wherein the accesses to the individual bits are sorted as a function of the address unit containing the applicable bit in such a manner that the accesses to all bits located in an address unit take place in sequence as a function of the address offset, independently of the signal containing the applicable bit.
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3.发明授权公开(公告)号：US11843514B2
公开(公告)日：2023-12-12
申请号：US17518288
申请日：2021-11-03
Inventor： Heiko Kalte , Dominik Lubeley
CPC classification number: H04L41/145 , H04L41/12 , H04L43/50
Abstract: A computer-implemented method for restructuring a predefined distributed real-time simulation network, wherein the simulation network has a plurality of network nodes and a plurality of data connections, wherein each network node has at least one data connection interface for connecting a data connection, wherein the network nodes are at least partially in communication via the data connections, and wherein during operation of the simulation network a simulation application is executed on at least one network node. The method permits a structure for the real-time simulation network to be automatically found in which the critical communication connections are reduced and avoided as much as possible by determining the topology of the simulation network so that topology information concerning the network nodes and the data connections between the network nodes is available by determining expected values for node data rates or node latencies for the network nodes of the simulation network.
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公开(公告)号：US11586793B2
公开(公告)日：2023-02-21
申请号：US16188893
申请日：2018-11-13
Inventor： Heiko Kalte , Dominik Lubeley
IPC: G06F30/331 , G06F30/34 , G06F30/327 , G06F9/30 , G06F11/36 , G06F30/333
Abstract: A method for creating an allocation map, wherein the allocation map is created based on an FPGA source code, wherein the source code uses at least a first signal at a first location, wherein at least a first register is mapped to the first signal, wherein in the allocation map, the first signal and the first register are listed as mapped to one another, wherein a second signal is used at a second location in the FPGA source code, wherein it is automatically detected that the value of the second signal can be determined from the value of the first signal according to a first calculation rule, wherein in the allocation map, the second signal, the first register and the first calculation rule are listed as mapped to one another.
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公开(公告)号：US11187748B2
公开(公告)日：2021-11-30
申请号：US16665019
申请日：2019-10-28
Inventor： Heiko Kalte , Dominik Lubeley
IPC: G01R31/3185 , G01R31/3183 , G01R31/3193
Abstract: A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.
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Patent Agency Ranking
公开(公告)号：US20190138310A1
公开(公告)日：2019-05-09
申请号：US16182637
申请日：2018-11-07
Inventor： Heiko Kalte , Dominik Lubeley
Abstract: A method for reading variables from a Field Programmable Gate Array (FPGA) at runtime includes: calculating, in the FPGA, a first variable, wherein the first variable is associated with a first shadow register and a second shadow register, and wherein the first variable is associated with a first measurement grid and with a second measurement grid; synchronously storing, at a first point in time, all variables associated with the first measurement grid in shadow registers associated with the respective variables; synchronously storing, at a second point in time, all variables associated with the second measurement grid in shadow registers associated with the respective variables; and reading out the shadow registers independently of one another.
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公开(公告)号：US11222159B2
公开(公告)日：2022-01-11
申请号：US17178787
申请日：2021-02-18
Inventor： Heiko Kalte , Dominik Lubeley
IPC: G06F30/30 , G06F30/392 , G06F30/34 , G06F30/347 , G06F30/337 , G06F30/343
Abstract: A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.
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公开(公告)号：US10706196B2
公开(公告)日：2020-07-07
申请号：US16207457
申请日：2018-12-03
Inventor： Dominik Lubeley , Heiko Kalte
IPC: G06F17/50 , G06F30/34 , G06F30/39 , G06F30/327 , G06F16/903 , G06F16/901 , G06F117/06
Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.
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公开(公告)号：US10671783B2
公开(公告)日：2020-06-02
申请号：US16207457
申请日：2018-12-03
Inventor： Dominik Lubeley , Heiko Kalte
IPC: G06F17/50 , G06F30/34 , G06F30/39 , G06F30/327 , G06F16/903 , G06F16/901 , G06F117/06
Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.
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公开(公告)号：US10224930B2
公开(公告)日：2019-03-05
申请号：US15964245
申请日：2018-04-27
Inventor： Dominik Lubeley , Marc Schlenger , Heiko Kalte
IPC: H03K19/003 , H03K19/017 , G01R31/317 , H03K19/0175
Abstract: A method for detecting the topology of electrical wiring between at least two field-programmable gate arrays (FPGAs) includes implementing a first receive register on a second interface pin; implementing a first send register on a first driver; activating the first driver via a first activation signal; emitting, by the first driver, a first signal, wherein the first signal is defined by the first send register; reading out, by a first receive register, whether the first signal is received at the second interface pin; and allocating the second interface pin to the first interface pin if the first signal from the first driver is received at the second interface pin.
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