Invention Grant
- Patent Title: Method of fabricating semiconductor structure with self-aligned spacers
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Application No.: US15599430Application Date: 2017-05-18
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Publication No.: US09870951B2Publication Date: 2018-01-16
- Inventor: Chih-Kai Hsu , Yu-Hsiang Hung , Ssu-I Fu , Jyh-Shyang Jenq
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: CN201510407826 20150713
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/78 ; H01L29/66 ; H01L21/768 ; H01L21/02 ; H01L23/535 ; H01L27/088 ; H01L23/485

Abstract:
A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The substrate between two gate structures is exposed. A silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer covers each gate structure and silicon oxide layer. Later, the nitride-containing material layer is etched to form a first self-aligned spacer on a sidewall of each gate structure and part of the silicon oxide layer is exposed, wherein the sidewalls are opposed to each other. Then, the exposed silicon oxide layer is removed to form a second self-aligned spacer. The first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate. Finally, a contact plug is formed in the recess.
Public/Granted literature
- US20170256459A1 METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED SPACERS Public/Granted day:2017-09-07
Information query
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