Invention Grant
- Patent Title: Method of manufacturing a device with MOS transistors
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Application No.: US15296205Application Date: 2016-10-18
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Publication No.: US09876032B2Publication Date: 2018-01-23
- Inventor: Sonarith Chhun , Emmanuel Josse , Gregory Bidal , Dominique Golanski , Francois Andrieu , Jerome Mazurier , Olivier Weber
- Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
- Applicant Address: FR Crolles FR Paris
- Assignee: STMicroelectronics (Crolles 2) SAS,Commissariat A L'Energie Atomique et aux Energies Alternatives
- Current Assignee: STMicroelectronics (Crolles 2) SAS,Commissariat A L'Energie Atomique et aux Energies Alternatives
- Current Assignee Address: FR Crolles FR Paris
- Agency: Gardere Wynne Sewell LLP
- Priority: FR1560090 20151022
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L27/092 ; H01L27/12 ; H01L21/8238 ; H01L29/66 ; H01L21/306 ; H01L21/84 ; H01L21/02 ; H01L29/08 ; H01L29/417 ; H01L21/8234 ; H01L29/16 ; H01L29/161

Abstract:
A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.
Public/Granted literature
- US20170117296A1 METHOD OF MANUFACTURING A DEVICE WITH MOS TRANSISTORS Public/Granted day:2017-04-27
Information query
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