Invention Grant
- Patent Title: Lane error detection and lane removal mechanism to reduce the probability of data corruption
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Application No.: US15075590Application Date: 2016-03-21
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Publication No.: US09887804B2Publication Date: 2018-02-06
- Inventor: Mark S. Birrittella
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Law Office of R. Alan Burnett, P.S
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G06F11/10 ; H04L1/00 ; H03M13/09 ; H04L1/18 ; H04L1/08 ; H04L1/16

Abstract:
Method, apparatus, and systems for detecting lane errors and removing errant lanes in multi-lane links. Data comprising link packets is split into a plurality of bitstreams and transmitted over respective lanes of a multi-lane link in parallel. The bitstream data is received at multiple receive lanes of a receiver port and processed to reassemble link packets and to calculate a CRC over the data received on each lane. The link packets include a transmitted CRC that is compared to a received CRC to detect link packet errors. Upon detection of a link packet error, per-lane or per transfer group CRC values are stored, and a retry request is issued to retransmit the bad packet. In conjunction with receipt of the retransmitted packet, per-lane or per transfer group CRC values are recalculated over the received data and compared with the stored per-lane or per transfer group CRC values to detect the lane causing the link packet error.
Public/Granted literature
- US20170026149A1 LANE ERROR DETECTION AND LANE REMOVAL MECHANISM TO REDUCE THE PROBABILITY OF DATA CORRUPTION Public/Granted day:2017-01-26
Information query
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