Invention Grant
- Patent Title: Loop vectorization methods and apparatus
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Application No.: US15005781Application Date: 2016-01-25
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Publication No.: US09898266B2Publication Date: 2018-02-20
- Inventor: Nalini Vasudevan , Jayashankar Bharadwaj , Christopher J. Hughes , Milind B. Girkar , Mark J. Charney , Robert Valentine , Victor W. Lee , Daehyun Kim , Albert Hartono , Sara S. Baghsorkhi
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Hanley, Flight & Zimmerman, LLC
- Main IPC: G06F9/45
- IPC: G06F9/45 ; G06F9/44 ; G06F9/38 ; G06F9/30

Abstract:
Loop vectorization methods and apparatus are disclosed. An example method includes prior to executing an original loop having iterations, analyzing, via a processor, the iterations of the original loop, identifying a dependency between a first one of the iterations of the original loop and a second one of the iterations of the original loop, after identifying the dependency, vectorizing a first group of the iterations of the original loop based on the identified dependency to form a vectorization loop, and setting a dynamic adjustment value of the vectorization loop based on the identified dependency.
Public/Granted literature
- US20160139897A1 LOOP VECTORIZATION METHODS AND APPARATUS Public/Granted day:2016-05-19
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