Invention Grant
- Patent Title: Fabrication method of coreless packaging substrate
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Application No.: US15334569Application Date: 2016-10-26
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Publication No.: US09899249B2Publication Date: 2018-02-20
- Inventor: Yu-Cheng Pai , Chun-Hsien Lin , Shih-Chao Chiu , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
- Applicant: Siliconware Precision Industries Co., Ltd.
- Applicant Address: TW Taichung
- Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee Address: TW Taichung
- Agency: Mintz Levin Cohn Ferris Glovsky and Popeo, P.C.
- Agent Peter F. Corless; Steven M. Jensen
- Priority: TW103124499A 20140717
- Main IPC: H01L21/683
- IPC: H01L21/683 ; H05K3/40 ; H01L23/498 ; H01L21/48 ; H05K3/46 ; H05K3/20 ; H01L23/00

Abstract:
A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.
Public/Granted literature
- US20170047240A1 FABRICATION METHOD OF CORELESS PACKAGING SUBSTRATE Public/Granted day:2017-02-16
Information query
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