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公开(公告)号：US20200328142A1
公开(公告)日：2020-10-15
申请号：US16538286
申请日：2019-08-12
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Don-Son Jiang , Nai-Hao Kao , Chih-Sheng Lin , Szu-Hsien Chen , Chih-Yuan Shih , Chia-Cheng Chen , Yu-Cheng Pai , Hsuan-Hao Mi
IPC: H01L23/498 , H01L23/14 , H01L23/367 , H01L23/00 , H01L21/48
Abstract: A package stack structure and a method for fabricating the same are provided. An electronic component is disposed on the topmost one of a plurality of organic material substrates, and no chip is disposed on the remaining organic material substrates. A predefined layer number of circuit layers are disposed in the organic material substrates, and distributes the thermal stress via the organic material substrates. Therefore, the bottommost one of the organic material substrates will not be separated from a circuit board due to CTE mismatch. Also a carrier component is provided.
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公开(公告)号：US20180247891A1
公开(公告)日：2018-08-30
申请号：US15968093
申请日：2018-05-01
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Shih-Chao Chiu , Chun-Hsien Lin , Ming-Chen Sun , Yu-Cheng Pai , Tzu-Chieh Shen
IPC: H01L23/522
CPC classification number: H01L23/5226 , H01L23/3121 , H01L23/49822 , H01L23/50 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/92 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/32225 , H01L2224/73253 , H01L2224/92242 , H01L2225/06513 , H01L2225/06517 , H01L2924/15153 , H01L2924/15313 , H01L2924/1579 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/014
Abstract: A method of fabricating a semiconductor package is provided, including providing a carrier provided having a circuit layer and a blocking member, forming on the carrier an encapsulating layer having a first surface and a second surface opposing the first surface and encapsulating the circuit layer and the blocking member, with the first surface coupled with the carrier, and removing the carrier and the blocking member to form in the encapsulating layer via the first surface thereof an opening for an electronic component to be received therein. Before the electronic component is disposed in the opening, the circuit layer and the electronic component can be tested in advance, in order to retire the defectives. Therefore, as a defective electronic component is prevented from being disposed in the opening, no defective semiconductor package will be fabricated.
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公开(公告)号：US20170309537A1
公开(公告)日：2017-10-26
申请号：US15648089
申请日：2017-07-12
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Shih-Chao Chiu , Chun-Hsien Lin , Yu-Cheng Pai , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC: H01L23/31 , H01L23/498 , H01L21/56 , H01L21/48
CPC classification number: H01L23/49861 , H01L21/4846 , H01L23/3128 , H01L23/49811 , H01L23/49827 , H01L2224/73204 , H01L2224/92125 , H01L2924/181 , H01L2924/00012
Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
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公开(公告)号：US09716060B2
公开(公告)日：2017-07-25
申请号：US14692769
申请日：2015-04-22
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Shih-Chao Chiu , Chun-Hsien Lin , Yu-Cheng Pai , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC: H01L23/498 , H05K3/00 , H05K3/32 , H05K1/18 , H01L23/538 , H01L23/00 , H05K1/02 , H05K3/10 , H05K3/46 , H01L23/31 , H01L21/683
CPC classification number: H01L23/49838 , H01L21/6835 , H01L23/3121 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2221/68318 , H01L2221/68345 , H01L2224/131 , H01L2224/13147 , H01L2224/16227 , H01L2224/16237 , H01L2224/26175 , H01L2224/2919 , H01L2224/32058 , H01L2224/32105 , H01L2224/32106 , H01L2224/32237 , H01L2224/73204 , H01L2224/81801 , H01L2224/83101 , H01L2924/15313 , H01L2924/18161 , H01L2924/19041 , H01L2924/19103 , H01L2924/19104 , H05K1/0231 , H05K1/185 , H05K1/186 , H05K1/189 , H05K3/0026 , H05K3/007 , H05K3/108 , H05K3/32 , H05K3/4682 , H05K2201/0376 , H05K2201/10515 , H05K2201/1053 , H05K2201/10674 , H05K2201/10977 , H01L2924/014 , H01L2924/00014 , H01L2924/0665
Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.
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5.发明申请公开(公告)号：US20160163621A1
公开(公告)日：2016-06-09
申请号：US14876404
申请日：2015-10-06
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Shih-Chao Chiu , Chun-Hsien Lin , Yu-Cheng Pai , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC: H01L23/498 , H01L21/56 , H01L23/31 , H01L21/48
CPC classification number: H01L23/49861 , H01L21/4846 , H01L23/3128 , H01L23/49811 , H01L23/49827 , H01L2224/73204 , H01L2224/92125 , H01L2924/181 , H01L2924/00012
Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
Abstract translation: 提供一种单层布线封装基板及其制造方法，该方法包括：在载体上形成具有与第一表面相对并与载体接触的第一表面和第二表面的布线层; 在所述载体上和所述布线层上形成绝缘体，所述绝缘体具有第一侧面，所述第一侧面具有第一开口，所述布线层的一部分从该第一开口露出;以及与所述第一侧相对的第二侧， 布线层表面; 并且在绝缘体的第二面和布线层的第二表面露出的同时移除载体。 因此，制造无芯封装基板，并且减小基板的整体厚度和成本。
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Patent Agency Ranking
公开(公告)号：US20160081186A1
公开(公告)日：2016-03-17
申请号：US14607572
申请日：2015-01-28
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chun-Hsien Lin , Shih-Chao Chiu , Yu-Cheng Pai , Tzu-Chieh Shen , Chia-Cheng Chen
CPC classification number: H05K3/007 , H05K1/0271 , H05K3/0026 , H05K3/188 , H05K3/28 , H05K3/4038 , H05K3/4682 , H05K2203/0152 , H05K2203/016 , H05K2203/1377
Abstract: The present invention provides a substrate structure and a method of fabricating the substrate substrure. The method includes: forming a first wiring layer on a first carrier, forming a dielectric layer on the first wiring layer, forming a second wiring layer on the dielectric layer, forming an insulating protection layer on the second wiring layer, forming a second carrier on the insulative protection layer, and remvoing the first carrier. The formation of the second carrier provides the substrate structure with adequate rigidity to avoid breakage or warpage such that the miniaturization requirement can be satisfied.
Abstract translation: 本发明提供一种衬底结构和制造衬底基底的方法。 该方法包括：在第一载体上形成第一布线层，在第一布线层上形成电介质层，在介电层上形成第二布线层，在第二布线层上形成绝缘保护层，在第二布线层上形成第二载体 绝缘保护层，并提供第一个载体。 第二载体的形成为基板结构提供足够的刚度以避免断裂或翘曲，从而可以满足小型化要求。
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公开(公告)号：US20160079170A1
公开(公告)日：2016-03-17
申请号：US14708249
申请日：2015-05-10
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yu-Cheng Pai , Wei-Chung Hsiao , Shih-Chao Chiu , Chun-Hsien Lin , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC: H01L23/538 , H01L21/56 , H01L21/48 , H01L25/00 , H01L23/00 , H01L25/065
CPC classification number: H01L23/5389 , H01L21/568 , H01L23/3128 , H01L24/19 , H01L24/96 , H01L2224/04105 , H01L2224/16227 , H01L2224/97 , H01L2924/15311 , H01L2224/81
Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
Abstract translation: 提供半导体封装结构及其制造方法。 半导体封装结构包括具有相对的第一和第二表面的封装体; 多个第一导电焊盘和形成在封装主体的第一表面上的多个第二导电焊盘; 嵌入在所述封装主体中并电连接到所述第一导电焊盘的半导体部件; 以及嵌入在所述封装主体中的多个导电元件，每个所述导电元件具有电连接到所述第二导电焊盘中的相应一个的第一端和与所述第一端相对并从所述封装体的所述第二表面露出的第二端 。 由于半导体部件嵌入封装主体中，所以半导体封装结构的厚度减小。
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公开(公告)号：US10141266B2
公开(公告)日：2018-11-27
申请号：US15621337
申请日：2017-06-13
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yu-Cheng Pai , Wei-Chung Hsiao , Shih-Chao Chiu , Chun-Hsien Lin , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC: H01L23/48 , H01L23/538 , H01L23/00 , H01L21/56 , H01L23/31
Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
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公开(公告)号：US10068842B2
公开(公告)日：2018-09-04
申请号：US15648089
申请日：2017-07-12
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Shih-Chao Chiu , Chun-Hsien Lin , Yu-Cheng Pai , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC: H01L23/498 , H01L21/48 , H01L23/31
Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
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公开(公告)号：US09905438B2
公开(公告)日：2018-02-27
申请号：US15466063
申请日：2017-03-22
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Ming-Chen Sun , Chun-Hsien Lin , Tzu-Chieh Shen , Shih-Chao Chiu , Yu-Cheng Pai
IPC: H01L21/48 , H01L23/00 , H01L23/498
CPC classification number: H01L21/4853 , H01L21/486 , H01L21/563 , H01L23/3114 , H01L23/3121 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/13082 , H01L2224/131 , H01L2224/16238 , H01L2224/81191 , H01L2224/81815 , H01L2224/8182 , H01L2924/15313 , H05K1/111 , H05K3/20 , H05K3/205 , H05K3/428 , H05K2201/0376 , H05K2201/09481 , H05K2201/09563 , H05K2201/10674 , H01L2924/00014 , H01L2924/014
Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.
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