- 专利标题: Fan-out chip package with dummy pattern and its fabricating method
-
申请号: US15245605申请日: 2016-08-24
-
公开(公告)号: US09899307B2公开(公告)日: 2018-02-20
- 发明人: Kuo-Ting Lin , Chia-Wei Chang
- 申请人: POWERTECH TECHNOLOGY INC.
- 申请人地址: TW Hsinchu County
- 专利权人: Powertech Technology Inc.
- 当前专利权人: Powertech Technology Inc.
- 当前专利权人地址: TW Hsinchu County
- 代理机构: JCIPRNET
- 优先权: TW104143306A 20151223
- 主分类号: H01L23/498
- IPC分类号: H01L23/498 ; H01L25/065 ; H01L21/48 ; H01L23/00 ; H01L21/56
摘要:
A fan-out chip package comprises a chip, an encapsulating layer, a first passivation layer, a redistribution wiring layer, a second passivation layer, and a plurality of vertical connectors. The encapsulation encapsulates the sides of the chip. The thickness of the encapsulation is the same as the thickness of the chip. The first passivation layer covers the active surface of the chip and the peripheral surface of the encapsulation. The redistribution layer is formed on the first passivation layer to extend the electrical connection of the chip to the peripheral surface of the encapsulation. The second passivation layer is formed on the first passivation layer. The vertical connectors are embedded in the encapsulation and the redistribution layer. The vertical connectors are only penetrate through the encapsulation protect the redistribution layer from damages.
公开/授权文献
- US20170186678A1 FAN-OUT CHIP PACKAGE AND ITS FABRICATING METHOD 公开/授权日:2017-06-29
信息查询
IPC分类: