- 专利标题: Reconfigurable delay circuit, delay monitor circuit using said delay circuit, variation compensation circuit, variation measurement method, and variation compensation method
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申请号: US14913309申请日: 2014-07-29
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公开(公告)号: US09899993B2公开(公告)日: 2018-02-20
- 发明人: Hidetoshi Onodera , Islam A. K. M Mahfuzul
- 申请人: JAPAN SCIENCE AND TECHNOLOGY AGENCY
- 申请人地址: JP Saitama
- 专利权人: JAPAN SCIENCE AND TECHNOLOGY AGENCY
- 当前专利权人: JAPAN SCIENCE AND TECHNOLOGY AGENCY
- 当前专利权人地址: JP Saitama
- 代理机构: Baker & Hostetler LLP
- 优先权: JP2013-169965 20130819
- 国际申请: PCT/JP2014/069976 WO 20140729
- 国际公布: WO2015/025682 WO 20150226
- 主分类号: H03K5/134
- IPC分类号: H03K5/134 ; G01R31/28 ; H03K5/00
摘要:
A delay circuit contains a first inversion circuit including a pull-up circuit and a pull-down circuit, and a second inversion circuit including a pull-up circuit and a pull-down circuit. The delay circuit further contains a first pass transistor connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node, a second pass transistor connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor connected in series between the input node and the pull-up circuit in the second inversion circuit, and a fourth pass transistor connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals applied to gates of the pass transistors.
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