- Patent Title: Method of manufacturing package substrate and semiconductor package
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Application No.: US15466063Application Date: 2017-03-22
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Publication No.: US09905438B2Publication Date: 2018-02-27
- Inventor: Ming-Chen Sun , Chun-Hsien Lin , Tzu-Chieh Shen , Shih-Chao Chiu , Yu-Cheng Pai
- Applicant: Siliconware Precision Industries Co., Ltd.
- Applicant Address: TW Taichung
- Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee Address: TW Taichung
- Agency: Mintz Levin Cohn Ferris Glovsky and Popeo, P.C.
- Agent Peter F. Corless; Steven M. Jensen
- Priority: TW103141137A 20141127
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/00 ; H01L23/498

Abstract:
A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.
Public/Granted literature
- US20170236725A1 METHOD OF MANUFACTURING PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE Public/Granted day:2017-08-17
Information query
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