Invention Grant
- Patent Title: Method of forming mask pattern, method of processing substrate, and method of fabricating element chips
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Application No.: US15252899Application Date: 2016-08-31
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Publication No.: US09905452B2Publication Date: 2018-02-27
- Inventor: Mitsuru Hiroshima , Atsushi Harikai
- Applicant: Panasonic Intellectual Property Management Co., Ltd.
- Applicant Address: JP Osaka
- Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee Address: JP Osaka
- Agency: Pearne & Gordon LLP
- Priority: JP2015-173729 20150903
- Main IPC: H01L21/683
- IPC: H01L21/683 ; H01L21/304 ; H01L21/78

Abstract:
In a method of fabricating element chips, a method of forming a mask pattern, and a method of processing a substrate, a process sequence is set such that developing in which the exposure-ended protection film is patterned is performed, after grinding in which the substrate is thinned by grinding a second surface opposite to a first surface to which a photosensitive protection film is pasted. Thereby, it is possible to perform the grinding for thinning in a state where the protection film is stable without being patterned, and to prevent the substrate or the protection film on which a mask pattern of the substrate is formed from being damaged at the time of the grinding, even in a case where a thin substrate of a wafer shape becomes a target.
Public/Granted literature
- US20170069522A1 METHOD OF FORMING MASK PATTERN, METHOD OF PROCESSING SUBSTRATE, AND METHOD OF FABRICATING ELEMENT CHIPS Public/Granted day:2017-03-09
Information query
IPC分类: