公开(公告)号：US11817323B2

公开(公告)日：2023-11-14

申请号：US17188005

申请日：2021-03-01

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai ,  Akihiro Itou

IPC: H01L21/311 ,  H01L21/78 ,  H01L21/683 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L21/31138 ,  H01L21/6836 ,  H01L21/78 ,  H01L21/02274 ,  H01L21/30655 ,  H01L2221/68327

Abstract: An etching method including: a preparation step of preparing a resin layer and an electronic component supported thereby; and a resin etching step of etching the resin layer. The electronic component has a first surface covered with a protective film, a second surface opposite thereto, and a sidewall therebetween. The second surface is facing the resin layer. The resin layer is larger than the electronic component when seen from the first surface side. The resin etching step includes: a deposition step of depositing a first film, using a first plasma, on a surface of the protective film and a surface of the resin layer; and a removal step of removing, using a second plasma, the first film deposited on the resin layer and at least part of the resin layer. The deposition and removal steps are alternately repeated, with the protective film allowed to continue to exist.

公开(公告)号：US11335564B2

公开(公告)日：2022-05-17

申请号：US16993466

申请日：2020-08-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akihiro Itou ,  Atsushi Harikai ,  Toshiyuki Takasaki ,  Shogo Okita

IPC: H01L21/3065 ,  H01L21/02

Abstract: An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist.

公开(公告)号：US10410924B2

公开(公告)日：2019-09-10

申请号：US15860827

申请日：2018-01-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko Karasaki ,  Hidefumi Saeki ,  Atsushi Harikai

IPC: H01L21/78 ,  H01L23/544 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/02 ,  B23K26/359 ,  H01L21/82 ,  H01L21/67 ,  H01L21/683 ,  B23K26/062 ,  H01J37/32 ,  B23K103/00

Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step for preparing a substrate including a semiconductor layer having first and second sides and a wiring layer on the first side thereof, the substrate having a plurality of dicing regions and element regions defined by the dicing regions, a scribing step for radiating a laser beam towards the first side of the wiring layer onto the dicing regions to form apertures exposing the semiconductor layer along the dicing regions, and a dicing step for dicing the substrate along the apertures into a plurality of the element chips, wherein the laser beam has a beam profile having a M-shaped distribution whose peripheral intensity is greater than a central intensity in a width direction of the laser beam along the dicing regions.

公开(公告)号：US11830758B2

公开(公告)日：2023-11-28

申请号：US17456908

申请日：2021-11-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Akihiro Itou

IPC: H01L21/3065 ,  H01L21/683 ,  H01J37/32

CPC classification number: H01L21/6836 ,  H01J37/32495 ,  H01J37/32862 ,  H01L21/3065

Abstract: A plasma processing method including: a process of placing a work piece on a stage provided in a chamber, the work piece including a substrate and a holding member having an adhesive layer on a surface and holding the substrate via the adhesive layer, and having an exposed portion where the adhesive layer is exposed outside the substrate; and a plasma etching process of etching the substrate with a plasma generated in the chamber, with the exposed portion exposed to the plasma. In response to occurrence of an interruption in the plasma etching process, a cleaning process of exposing a surface of the substrate to a plasma containing an oxidizing gas is performed, and then the plasma etching process is resumed.

公开(公告)号：US10923362B2

公开(公告)日：2021-02-16

申请号：US16939492

申请日：2020-07-27

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Noriyuki Matsubara ,  Shogo Okita ,  Hidehiko Karasaki

IPC: H01L21/20 ,  H01L21/306 ,  G03F7/038 ,  G03F7/40 ,  H01L21/78 ,  H01L29/06 ,  H01L21/311 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/82 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/308 ,  H01L21/683 ,  H01J37/00 ,  H01L23/00

Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.

公开(公告)号：US10242914B2

公开(公告)日：2019-03-26

申请号：US15952342

申请日：2018-04-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Noriyuki Matsubara ,  Atsushi Harikai ,  Akihiro Itou

IPC: H01L21/027 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  G03F7/20 ,  G03F7/32 ,  G03F7/039 ,  G03F7/16 ,  G03F7/09 ,  H01J37/32

Abstract: A semiconductor chip manufacturing method includes forming a mask on a surface of a semiconductor wafer, forming an opening on the mask, exposing a dividing region of the semiconductor wafer, a rear surface of the semiconductor wafer is held by a dicing tape via an adhesive layer, singulating the semiconductor wafer into a plurality of semiconductor chips by etching the semiconductor wafer exposed to the opening with a first plasma until the semiconductor wafer reaches a rear surface, removing the mask so that the plurality of element chips from which the mask is removed are held by the holding sheet via the adhesive layer.At the time of removing the mask, the mask is removed from an alkaline developer having a dissolution rate of the mask larger than a dissolution rate of the adhesive layer.

公开(公告)号：US10177063B2

公开(公告)日：2019-01-08

申请号：US15426181

申请日：2017-02-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Bunzi Mizuno ,  Mitsuru Hiroshima ,  Shogo Okita ,  Noriyuki Matsubara ,  Atsushi Harikai

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/268 ,  H01L21/311 ,  H01L21/56 ,  H01L21/78 ,  H01L23/544 ,  H01L21/683 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/67

Abstract: A method for manufacturing an element chip includes a protection film stacking step of staking a protection film to the element region, and the dividing region, the part of the exposed second damaged region and a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region by exposing the substrate to second plasma and remaining the protection film for covering the part of the second damaged region. Furthermore, the method for manufacturing an element chip includes a plasma dicing step of dividing the substrate to a plurality of element chips by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.

公开(公告)号：US09905452B2

公开(公告)日：2018-02-27

申请号：US15252899

申请日：2016-08-31

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Mitsuru Hiroshima ,  Atsushi Harikai

IPC: H01L21/683 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L21/6836 ,  H01L21/304 ,  H01L21/3081 ,  H01L21/6835 ,  H01L21/78 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: In a method of fabricating element chips, a method of forming a mask pattern, and a method of processing a substrate, a process sequence is set such that developing in which the exposure-ended protection film is patterned is performed, after grinding in which the substrate is thinned by grinding a second surface opposite to a first surface to which a photosensitive protection film is pasted. Thereby, it is possible to perform the grinding for thinning in a state where the protection film is stable without being patterned, and to prevent the substrate or the protection film on which a mask pattern of the substrate is formed from being damaged at the time of the grinding, even in a case where a thin substrate of a wafer shape becomes a target.

公开(公告)号：US09779986B2

公开(公告)日：2017-10-03

申请号：US15245139

申请日：2016-08-23

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Noriyuki Matsubara ,  Hideo Kanou ,  Mitsuru Hiroshima ,  Syouzou Watanabe ,  Toshihiro Wada

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L21/76826 ,  H01L21/78

Abstract: Provided is a plasma treatment method including: placing a substrate carrier holding a substrate on a stage; adjusting a distance between a cover and the stage to a first distance in which the cover covers a frame without coming into contact with the substrate carrier; performing a plasma treatment on the substrate placed on the stage after the adjusting of the distance; carrying the substrate together with the substrate carrier out from a reaction chamber after the performing of the plasma treatment; and removing an adhered substance adhered to the cover by generating plasma in the inside of the reaction chamber after the carrying of the substrate, in which the distance between the cover and the stage in the removing of the adhered substance is a second distance greater than the first distance.

公开(公告)号：US09698073B2

公开(公告)日：2017-07-04

申请号：US15264921

申请日：2016-09-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Noriyuki Matsubara ,  Mitsuru Hiroshima ,  Mitsuhiro Okune

IPC: H01L21/318 ,  H01L21/78 ,  H01L21/683 ,  H01L23/31 ,  H01L21/02 ,  H01L23/29

CPC classification number: H01L23/3185 ,  H01L21/0212 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/293 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: In a plasma processing step in a method of manufacturing an element chip in which a plurality of element chips are manufactured by dividing a substrate, which has a plurality of element regions, the substrate is divided into element chips by exposing the substrate to first plasma. In a protection film forming step of forming a protection film covering a side surface and a second surface by exposing the element chips to second plasma of which raw material gas is mixed gas of carbon fluoride and helium, protection film forming conditions are set such that a thickness of a second protection film of the second surface is greater than a thickness of a first protection film of the side surface.