Invention Grant
- Patent Title: Three-dimensionally integrated circuit devices including oxidation suppression layers
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Application No.: US15426081Application Date: 2017-02-07
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Publication No.: US09911745B2Publication Date: 2018-03-06
- Inventor: Dong-Sik Lee , Youngwoo Kim , Jinhyun Shin , Jung Hoon Lee
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Ward and Smith, P.A.
- Priority: KR10-2015-0167754 20151127
- Main IPC: H01L27/11551
- IPC: H01L27/11551 ; H01L27/11573 ; H01L27/11582 ; H01L27/11 ; H01L27/11556 ; H01L27/108 ; H01L27/11529 ; H01L27/112 ; H01L27/11526 ; H01L27/115 ; H01L21/8234 ; H01L27/11597

Abstract:
A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.
Public/Granted literature
- US20170148804A1 Three-Dimensionally Integrated Circuit Devices Including Oxidation Suppression Layers Public/Granted day:2017-05-25
Information query
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