- Patent Title: Semiconductor device with electrical overstress (EOS) protection
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Application No.: US13871526Application Date: 2013-04-26
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Publication No.: US09917080B2Publication Date: 2018-03-13
- Inventor: Andrew P. Ritenour
- Applicant: RF Micro Devices, Inc.
- Applicant Address: US NC Greensboro
- Assignee: Qorvo US. Inc.
- Current Assignee: Qorvo US. Inc.
- Current Assignee Address: US NC Greensboro
- Agency: Withrow & Terranova, P.L.L.C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/06 ; H01L27/02 ; H01L29/778 ; H01L29/20

Abstract:
A semiconductor device with electrical overstress (EOS) protection is disclosed. The semiconductor device includes a semi-insulating layer, a first contact disposed onto the semi-insulating layer, and a second contact disposed onto the semi-insulating layer. A passivation layer is disposed onto the semi-insulating layer. The passivation layer has a dielectric strength that is greater than that of the semi-insulating layer to ensure that a voltage breakdown occurs within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer.
Public/Granted literature
- US20140054596A1 SEMICONDUCTOR DEVICE WITH ELECTRICAL OVERSTRESS (EOS) PROTECTION Public/Granted day:2014-02-27
Information query
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