Invention Grant
- Patent Title: Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing
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Application No.: US14815314Application Date: 2015-07-31
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Publication No.: US09922866B2Publication Date: 2018-03-20
- Inventor: Stephen W. Bedell , Stephan A. Cohen , Joel P. de Souza , Karen A. Nummy , Daniel J. Poindexter , Devendra K. Sadana
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Louis J. Percello, Esq.
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L29/66 ; H01L21/762 ; H01L21/324
Abstract:
A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.
Public/Granted literature
- US20170033001A1 ENHANCING ROBUSTNESS OF SOI SUBSTRATE CONTAINING A BURIED N+ SILICON LAYER FOR CMOS PROCESSING Public/Granted day:2017-02-02
Information query
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