Invention Grant
- Patent Title: Semiconductor device including power MOS transistor
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Application No.: US15455410Application Date: 2017-03-10
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Publication No.: US09923091B2Publication Date: 2018-03-20
- Inventor: Hiroyoshi Kudou , Taro Moriya
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2016-049572 20160314
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/66
Abstract:
An n-channel power MOS transistor having a gate electrode is formed in an element formation region defined in a semiconductor substrate. A p-type guard ring region is formed in a terminal region. A plurality of p-type column regions are formed from the bottom of the p-type base region to a further deeper position. The column region located in the outermost periphery and the p−-type guard ring region are spaced apart from each other by a distance. A gate electrode lead-out portion electrically coupled to the gate electrode is formed in the p−-type guard ring region.
Public/Granted literature
- US20170263755A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2017-09-14
Information query
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