Invention Grant
- Patent Title: Techniques for detecting false positive return-oriented programming attacks
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Application No.: US14582114Application Date: 2014-12-23
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Publication No.: US09940484B2Publication Date: 2018-04-10
- Inventor: Koichi Yamada , Palanivelrajan Shanmugavelayutham , Lior Malka , Ashish Bijlani
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F21/56
- IPC: G06F21/56 ; G06F21/80 ; G06F12/14 ; G06F13/42 ; G06F13/40 ; G06F13/38 ; G06F21/85 ; G06F21/55 ; G06F21/54

Abstract:
Various embodiments are generally directed to an apparatus, method and other techniques to determine whether a target address of a register for an execution instruction is valid or invalid based on a comparison between the target address and one or more valid target addresses stored in a storage, increase a number of invalid target addresses if the target address is invalid, and determine whether the number of invalid target addresses is greater than an invalid target address threshold. Various embodiments may also include initiating a security measure to prevent a security breach if the number of invalid target addresses is greater than the invalid target address threshold or executing the execution instruction if the number of invalid target addresses is less than or equal to the invalid target address threshold.
Public/Granted literature
- US20160180115A1 TECHNIQUES FOR DETECTING FALSE POSITIVE RETURN-ORIENTED PROGRAMMING ATTACKS Public/Granted day:2016-06-23
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